Assignee
AMPERE COMPUTING LLC
US·72 granted patents·35 pending applications·102 citations·filing 2013–2025
Top patents by PatentIndex Score
107 records- 0197US12204410B2Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Jan 21, 2025·14 cites·25 claims
- 0296US10348281B1Clock control based on voltage associated with a microprocessorAMPERE COMPUTING LLC·Filed 2016·Granted Jul 9, 2019·20 cites·15 claims
- 0394US11880686B2Devices transferring cache lines, including metadata on external linksAMPERE COMPUTING LLC·Filed 2022·Granted Jan 23, 2024·2 cites·22 claims
- 0494US10145868B2Self-referenced on-die voltage droop detectorAMPERE COMPUTING LLC·Filed 2016·Granted Dec 4, 2018·7 cites·18 claims
- 0592US12423108B2Devices transferring cache lines, including metadata on external linksAMPERE COMPUTING LLC·Filed 2023·Granted Sep 23, 2025·1 cites·20 claims
- 0692US10162373B1Variation immune on-die voltage droop detectorAMPERE COMPUTING LLC·Filed 2017·Granted Dec 25, 2018·11 cites·20 claims
- 0790US12019565B2Advanced initialization bus (AIB)AMPERE COMPUTING LLC·Filed 2022·Granted Jun 25, 2024·4 cites·18 claims
- 0889US11934834B2Instruction scheduling in a processor using operation source parent trackingAMPERE COMPUTING LLC·Filed 2021·Granted Mar 19, 2024·2 cites·20 claims
- 0988US12007896B2Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based systemAMPERE COMPUTING LLC·Filed 2022·Granted Jun 11, 2024·3 cites·17 claims
- 1086US11934263B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2022·Granted Mar 19, 2024·1 cites·24 claims
- 1185US11481270B1Method and system for sequencing data checks in a packetAMPERE COMPUTING LLC·Filed 2021·Granted Oct 25, 2022·2 cites·18 claims
- 1284US10372615B1Data management for cache memoryAMPERE COMPUTING LLC·Filed 2017·Granted Aug 6, 2019·3 cites·19 claims
- 1384US10318696B1Efficient techniques for process variation reduction for static timing analysisAMPERE COMPUTING LLC·Filed 2016·Granted Jun 11, 2019·7 cites·20 claims
- 1484US10318676B2Techniques for statistical frequency enhancement of statically timed designsAMPERE COMPUTING LLC·Filed 2017·Granted Jun 11, 2019·6 cites·13 claims
- 1581US11947454B2Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based systemAMPERE COMPUTING LLC·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 1681US11880306B2Apparatus, system, and method for configuring a configurable combined private and shared cacheAMPERE COMPUTING LLC·Filed 2022·Granted Jan 23, 2024·1 cites·14 claims
- 1779US10191868B2Priority framework for a computing deviceAMPERE COMPUTING LLC·Filed 2018·Granted Jan 29, 2019·2 cites·20 claims
- 1878US2025231236A1Component die validation built-in self-test (vbist) engineAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 1978US2025356019A1Method and system for patching a boot processAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 2077US9965419B1Multiple-queue integer coalescing mapping algorithm with shared based timeAMPERE COMPUTING LLC·Filed 2016·Granted May 8, 2018·3 cites·21 claims
- 2176US9971693B2Prefetch tag for eviction promotionAMPERE COMPUTING LLC·Filed 2015·Granted May 15, 2018·2 cites·20 claims
- 2275US12314130B2Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilizationAMPERE COMPUTING LLC·Filed 2024·Granted May 27, 2025·0 cites·17 claims
- 2372US2026023116A1Integrated circuits including error protection of fields in transferred information and field-based error signals and related methodsAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 2471US12282064B2Component die validation built-in self-test (VBIST) engineAMPERE COMPUTING LLC·Filed 2022·Granted Apr 22, 2025·0 cites·35 claims
- 2570US12549479B2Apparatus and method of routing a request in a mesh networkAMPERE COMPUTING LLC·Filed 2024·Granted Feb 10, 2026·0 cites·17 claims
- 2670US12411778B2Advanced initialization bus (AIB)AMPERE COMPUTING LLC·Filed 2024·Granted Sep 9, 2025·0 cites·18 claims
- 2770US12241932B2Method and system for testing semiconductor circuitsAMPERE COMPUTING LLC·Filed 2022·Granted Mar 4, 2025·0 cites·22 claims
- 2870US2024370273A1Multi-socket computing system employing a parallelized boot architecture with partially concurrent processor boot-up operations, and related methodsAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 2969US12385975B1Integrated circuits including error protection of fields in transferred information and field-based error signals and related methodsAMPERE COMPUTING LLC·Filed 2024·Granted Aug 12, 2025·0 cites·31 claims
- 3069US2025189580A1Method and system for testing semiconductor circuitsAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
- 3168US10439960B1Memory page request for optimizing memory page latency associated with network nodesAMPERE COMPUTING LLC·Filed 2016·Granted Oct 8, 2019·2 cites·19 claims
- 3268US10210096B2Multi-stage address translation for a computing deviceAMPERE COMPUTING LLC·Filed 2013·Granted Feb 19, 2019·2 cites·23 claims
- 3367US12474848B2Techniques for memory resource control using memory resource partitioning and monitoringAMPERE COMPUTING LLC·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 3466US12058044B1Apparatus and method of routing a request in a mesh networkAMPERE COMPUTING LLC·Filed 2023·Granted Aug 6, 2024·0 cites·12 claims
- 3565US11868209B2Method and system for sequencing data checks in a packetAMPERE COMPUTING LLC·Filed 2022·Granted Jan 9, 2024·0 cites·20 claims
- 3664US12554640B2Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based systemAMPERE COMPUTING LLC·Filed 2024·Granted Feb 17, 2026·0 cites·20 claims
- 3764US12175243B2Hardware micro-fused memory operationsAMPERE COMPUTING LLC·Filed 2019·Granted Dec 24, 2024·1 cites·13 claims
- 3863US11822487B2Flexible storage and optimized search for multiple page sizes in a translation lookaside bufferAMPERE COMPUTING LLC·Filed 2021·Granted Nov 21, 2023·0 cites·18 claims
- 3962US10205666B2End-to-end flow control in system on chip interconnectsAMPERE COMPUTING LLC·Filed 2013·Granted Feb 12, 2019·2 cites·20 claims
- 4062US2024005004A1Method and system for patching a boot processAMPERE COMPUTING LLC·Filed 2022·Application pending·0 cites
- 4161US11386016B2Flexible storage and optimized search for multiple page sizes in a translation lookaside bufferAMPERE COMPUTING LLC·Filed 2019·Granted Jul 12, 2022·0 cites·38 claims
- 4260US12056497B2Multi-socket computing system employing a parallelized boot architecture with partially concurrent processor boot-up operations, and related methodsAMPERE COMPUTING LLC·Filed 2022·Granted Aug 6, 2024·0 cites·25 claims
- 4360US12056052B2Data L2 cache with split accessAMPERE COMPUTING LLC·Filed 2022·Granted Aug 6, 2024·0 cites·20 claims
- 4460US11513798B1Implementation of load acquire/store release instructions using load/store operation with DMB operationAMPERE COMPUTING LLC·Filed 2019·Granted Nov 29, 2022·0 cites·24 claims
- 4559US11586537B2Method, apparatus, and system for run-time checking of memory tags in a processor-based systemAMPERE COMPUTING LLC·Filed 2021·Granted Feb 21, 2023·0 cites·33 claims
- 4659US10819783B1Managing a data packet for an operating system associated with a multi-node systemAMPERE COMPUTING LLC·Filed 2016·Granted Oct 27, 2020·1 cites·20 claims
- 4759US2026056888A1Virtual to physical partial translation cache for accelerating virtualized page table walksAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 4858US12346264B2Performing instruction fetch pipeline synchronization (IFPS) in processor-based devicesAMPERE COMPUTING LLC·Filed 2023·Granted Jul 1, 2025·0 cites·20 claims
- 4958US10083131B2Generating and/or employing a descriptor associated with a memory translation tableAMPERE COMPUTING LLC·Filed 2014·Granted Sep 25, 2018·2 cites·20 claims
- 5058US2025147572A1Method, apparatus, and system for calibrating a processor power level estimateAMPERE COMPUTING LLC·Filed 2025·Application pending·0 cites
Showing the top 50 of 107 patent records by PatentIndex Score.
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