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ARTERIS INC

US86 patents

Top patents by PatentIndex Score

US9940423B2Apr 10, 2018

Editing a NoC topology on top of a floorplan

ARTERIS INC23 citations94

US11449655B2Sep 20, 2022

Synthesis of a network-on-chip (NoC) using performance constraints and objectives

ARTERIS INC18 citations93

US11121933B2Sep 14, 2021

Optimization of parameters for synthesis of a topology using a discriminant function module

ARTERIS INC19 citations89

US9542316B1Jan 10, 2017

System and method for adaptation of coherence models between agents

ARTERIS INC12 citations82

US10528421B2Jan 7, 2020

Protection scheme conversion

ARTERIS INC9 citations81

US11210445B1Dec 28, 2021

System and method for interface protection

ARTERIS INC6 citations79

US10949585B1Mar 16, 2021

System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design

ARTERIS INC10 citations77

US10268794B2Apr 23, 2019

Editing a NoC topology on top of a floorplan

ARTERIS INC2 citations73

US11836427B2Dec 5, 2023

Constraints and objectives used in synthesis of a network-on-chip (NoC)

ARTERIS INC1 citations72

US11665776B2May 30, 2023

System and method for synthesis of a network-on-chip for deadlock-free transformation

ARTERIS INC2 citations72

US11657203B2May 23, 2023

Multi-phase topology synthesis of a network-on-chip (NoC)

ARTERIS INC2 citations72

US11601357B2Mar 7, 2023

System and method for generation of quality metrics for optimization tasks in topology synthesis of a network

ARTERIS INC2 citations72

US10902166B2Jan 26, 2021

System and method for isolating faults in a resilient system

ARTERIS INC5 citations71

US10877839B2Dec 29, 2020

Recovery of a coherent system in the presence of an uncorrectable error

ARTERIS INC3 citations71

US10146615B2Dec 4, 2018

Recovery of a system directory after detection of uncorrectable error

ARTERIS INC4 citations71

US9652391B2May 16, 2017

Compression of hardware cache coherent addresses

ARTERIS INC3 citations71

US12237980B2Feb 25, 2025

Topology synthesis of a network-on-chip (NoC)

ARTERIS INC2 citations70

US10452499B2Oct 22, 2019

Redundancy for cache coherence systems

ARTERIS INC1 citations70

US12164428B2Dec 10, 2024

System and method for event messages in a cache coherent interconnect

ARTERIS INC2 citations69

US11847394B2Dec 19, 2023

System and method for using interface protection parameters

ARTERIS INC2 citations68

US11675942B2Jun 13, 2023

Optimization of parameters for synthesis of a topology using a discriminant function module

ARTERIS INC2 citations68

US10719651B2Jul 21, 2020

Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocks

ARTERIS INC2 citations67

US10592358B2Mar 17, 2020

Functional interconnect redundancy in cache coherent systems

ARTERIS INC1 citations67

US12524590B2Jan 13, 2026

Synthesis of a network-on-chip (NoC) for insertion of pipeline stages

ARTERIS INC0 citations62

US12517829B1Jan 6, 2026

Processing writes to multiple targets in a directory-based cache coherent electronic system

ARTERIS INC0 citations62

US12348382B2Jul 1, 2025

Incremental topology modification of a network-on-chip

ARTERIS INC0 citations62

US12204833B2Jan 21, 2025

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

ARTERIS INC0 citations62

US12184499B2Dec 31, 2024

System and method for editing a network-on-chip (NOC)

ARTERIS INC0 citations62

US12135928B2Nov 5, 2024

Constraints and objectives used in synthesis of a network-on-chip (NoC)

ARTERIS INC0 citations62

US11956127B2Apr 9, 2024

Incremental topology modification of a network-on-chip

ARTERIS INC0 citations62

US11784909B2Oct 10, 2023

Quality metrics for optimization tasks in generation of a network

ARTERIS INC0 citations62

US11748535B2Sep 5, 2023

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

ARTERIS INC0 citations62

US11082327B2Aug 3, 2021

System and method for computational transport network-on-chip (NoC)

ARTERIS INC1 citations62

US11805080B2Oct 31, 2023

System and method for data loss and data latency management in a network-on-chip with buffered switches

ARTERIS INC0 citations60

US11757798B2Sep 12, 2023

Management of a buffered switch having virtual channels for data transmission within a network

ARTERIS INC0 citations60

US11513892B2Nov 29, 2022

System and method for using a directory to recover a coherent system from an uncorrectable error

ARTERIS INC0 citations60

US11507510B2Nov 22, 2022

Method for using victim buffer in cache coherent systems

ARTERIS INC0 citations60

US11385957B2Jul 12, 2022

System for memory access bandwidth management using ECC

ARTERIS INC0 citations60

US11294757B2Apr 5, 2022

System and method for advanced detection of failures in a network-on-chip

ARTERIS INC0 citations60

US11237965B2Feb 1, 2022

Configurable snoop filters for cache coherent systems

ARTERIS INC1 citations60

US11176297B2Nov 16, 2021

Detection and isolation of faults to prevent propagation of faults in a resilient system

ARTERIS INC0 citations60

US11100269B2Aug 24, 2021

System and method for estimation of chip floorplan activity

ARTERIS INC0 citations60

US11080191B2Aug 3, 2021

Configurable snoop filters for cache coherent systems

ARTERIS INC1 citations60

US10452272B2Oct 22, 2019

System to reduce directory information storage

ARTERIS INC1 citations60

US10452266B2Oct 22, 2019

Directory storage control for commonly used patterns

ARTERIS INC1 citations60

US10025677B2Jul 17, 2018

Redundancy for cache coherence systems

ARTERIS INC1 citations60

US12411801B2Sep 9, 2025

System and method for transaction broadcast in a network on chip

ARTERIS INC0 citations59

Showing the top 50 of 86 patents by PatentIndex Score.

ARTERIS INC

Top patents by PatentIndex Score

Editing a NoC topology on top of a floorplan

Synthesis of a network-on-chip (NoC) using performance constraints and objectives

Physically aware topology synthesis of a network

System and method for incremental topology synthesis of a network-on-chip

Network-on-chip (NoC) topology generation

Optimization of parameters for synthesis of a topology using a discriminant function module

System and method for adaptation of coherence models between agents

Protection scheme conversion

System and method for interface protection

System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design

Editing a NoC topology on top of a floorplan

Constraints and objectives used in synthesis of a network-on-chip (NoC)

System and method for synthesis of a network-on-chip for deadlock-free transformation

Multi-phase topology synthesis of a network-on-chip (NoC)

System and method for generation of quality metrics for optimization tasks in topology synthesis of a network

System and method for isolating faults in a resilient system

Recovery of a coherent system in the presence of an uncorrectable error

Recovery of a system directory after detection of uncorrectable error

Compression of hardware cache coherent addresses

Topology synthesis of a network-on-chip (NoC)

Redundancy for cache coherence systems

System and method for event messages in a cache coherent interconnect

System and method for using interface protection parameters

Optimization of parameters for synthesis of a topology using a discriminant function module

Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocks

Functional interconnect redundancy in cache coherent systems

Synthesis of a network-on-chip (NoC) for insertion of pipeline stages

Processing writes to multiple targets in a directory-based cache coherent electronic system

Incremental topology modification of a network-on-chip

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

System and method for editing a network-on-chip (NOC)

Constraints and objectives used in synthesis of a network-on-chip (NoC)

Incremental topology modification of a network-on-chip

Quality metrics for optimization tasks in generation of a network

System and method to generate a network-on-chip (NoC) description using incremental topology synthesis

System and method for computational transport network-on-chip (NoC)

System and method for data loss and data latency management in a network-on-chip with buffered switches

Management of a buffered switch having virtual channels for data transmission within a network

System and method for using a directory to recover a coherent system from an uncorrectable error

Method for using victim buffer in cache coherent systems

System for memory access bandwidth management using ECC

System and method for advanced detection of failures in a network-on-chip

Configurable snoop filters for cache coherent systems

Detection and isolation of faults to prevent propagation of faults in a resilient system

System and method for estimation of chip floorplan activity

Configurable snoop filters for cache coherent systems

System to reduce directory information storage

Directory storage control for commonly used patterns

Redundancy for cache coherence systems

System and method for transaction broadcast in a network on chip