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ATRENTA INC
US38 patents
Top patents by PatentIndex Score
US7152216B2Dec 19, 2006
Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains
ATRENTA INC23 citations89
US7076748B2Jul 11, 2006
Identification and implementation of clock gating in the design of integrated circuits
ATRENTA INC47 citations89
US7073146B2Jul 4, 2006
Method for clock synchronization validation in integrated circuit design
ATRENTA INC30 citations89
US8839171B1Sep 16, 2014
Method of global design closure at top level and driving of downstream implementation flow
ATRENTA INC26 citations87
US7650581B2Jan 19, 2010
Method for modeling and verifying timing exceptions
ATRENTA INC11 citations83
US8656326B1Feb 18, 2014
Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design
ATRENTA INC7 citations82
US8856706B2Oct 7, 2014
System and method for metastability verification of circuits of an integrated circuit
ATRENTA INC7 citations81
US6993733B2Jan 31, 2006
Apparatus and method for handling of multi-level circuit design data
ATRENTA INC12 citations81
US7349835B2Mar 25, 2008
Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuits
ATRENTA INC10 citations80
US8533647B1Sep 10, 2013
Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design
ATRENTA INC13 citations79
US7536662B2May 19, 2009
Method for recognizing and verifying FIFO structures in integrated circuit designs
ATRENTA INC11 citations79
US8930863B2Jan 6, 2015
System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist
ATRENTA INC11 citations78
US7216321B2May 8, 2007
Pattern recognition in an integrated circuit design
ATRENTA INC11 citations78
US6876934B2Apr 5, 2005
Method for determining fault coverage from RTL description
ATRENTA INC14 citations76
US7451427B2Nov 11, 2008
Bus representation for efficient physical synthesis of integrated circuit designs
ATRENTA INC7 citations72
US7506292B2Mar 17, 2009
Method for clock synchronization validation in integrated circuit design
ATRENTA INC6 citations71
US8863058B2Oct 14, 2014
Characterization based buffering and sizing for system performance optimization
ATRENTA INC5 citations67
US8782582B1Jul 15, 2014
Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
ATRENTA INC4 citations66
US7277840B2Oct 2, 2007
Method for detecting bus contention from RTL description
ATRENTA INC9 citations65
US8806401B1Aug 12, 2014
System and methods for reasonable functional verification of an integrated circuit design
ATRENTA INC6 citations64
US8732647B1May 20, 2014
Method for creating physical connections in 3D integrated circuits
ATRENTA INC4 citations64
US7941679B2May 10, 2011
Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit design
ATRENTA INC5 citations63
US8881075B2Nov 4, 2014
Method for measuring assertion density in a system of verifying integrated circuit design
ATRENTA INC2 citations61
US8745567B1Jun 3, 2014
Efficient apparatus and method for analysis of RTL structures that cause physical congestion
ATRENTA INC4 citations61
US7546559B2Jun 9, 2009
Method of optimization of clock gating in integrated circuit designs
ATRENTA INC6 citations60
US7712061B2May 4, 2010
Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits
ATRENTA INC4 citations59
US8042085B2Oct 18, 2011
Method for compaction of timing exception paths
ATRENTA INC5 citations57
US8782587B2Jul 15, 2014
Systems and methods for generating a higher level description of a circuit design based on connectivity strengths
ATRENTA INC3 citations55
US7882483B2Feb 1, 2011
Method for checking constraints equivalence of an integrated circuit design
ATRENTA INC5 citations54
US8756466B2Jun 17, 2014
Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test
ATRENTA INC1 citations52
US8677295B1Mar 18, 2014
Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design
ATRENTA INC1 citations50
US8984457B2Mar 17, 2015
System and method for a hybrid clock domain crossing verification
ATRENTA INC0 citations49
US8984469B2Mar 17, 2015
System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption
ATRENTA INC1 citations48
US8813003B2Aug 19, 2014
System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependency
ATRENTA INC0 citations48
US8635578B1Jan 21, 2014
System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption
ATRENTA INC1 citations48
US8788993B2Jul 22, 2014
Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) design
ATRENTA INC1 citations46
US8656328B1Feb 18, 2014
System and method for abstraction of a circuit portion of an integrated circuit
ATRENTA INC0 citations35
US8739087B1May 27, 2014
System and method for large multiplexer identification and creation in a design of an integrated circuit
ATRENTA INC0 citations33