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BLATCHFORD JAMES WALTER
US10 patents
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US8461038B2Jun 11, 2013
Two-track cross-connects in double-patterned metal layers using a forbidden zone
BLATCHFORD JAMES WALTER5 citations72
US8603905B2Dec 10, 2013
Dual alignment strategy for optimizing contact layer alignment
BLATCHFORD JAMES WALTER2 citations62
US8575020B2Nov 5, 2013
Pattern-split decomposition strategy for double-patterned lithography process
BLATCHFORD JAMES WALTER3 citations62
US8455180B2Jun 4, 2013
Gate CD control using local design on both sides of neighboring dummy gate level features
BLATCHFORD JAMES WALTER1 citations62
US10741489B2Aug 11, 2020
Rectangular via for ensuring via yield in the absence of via redundancy
BLATCHFORD JAMES WALTER0 citations51
US8751977B2Jun 10, 2014
Method for generating ultra-short-run-length dummy poly features
BLATCHFORD JAMES WALTER0 citations51
US8607170B2Dec 10, 2013
Perturbational technique for co-optimizing design rules and illumination conditions for lithography process
BLATCHFORD JAMES WALTER0 citations51
US8580675B2Nov 12, 2013
Two-track cross-connect in double-patterned structure using rectangular via
BLATCHFORD JAMES WALTER1 citations51
US8584053B2Nov 12, 2013
Manufacturability enhancements for gate patterning process using polysilicon sub layer
BLATCHFORD JAMES WALTER1 citations51
US8138074B1Mar 20, 2012
ICs with end gates having adjacent electrically connected field poly
BLATCHFORD JAMES WALTER0 citations41