Assignee
CAPRIOLI PAUL
US11 patents
Top patents by PatentIndex Score
US8161273B2Apr 17, 2012
Method and apparatus for programmatically rewinding a register inside a transaction
CAPRIOLI PAUL54 citations98
US8151084B2Apr 3, 2012
Using address and non-address information for improved index generation for cache memories
CAPRIOLI PAUL6 citations84
US8732438B2May 20, 2014
Anti-prefetch instruction
CAPRIOLI PAUL9 citations83
US9330020B2May 3, 2016
System, apparatus, and method for transparent page level instruction translation
CAPRIOLI PAUL6 citations73
US8484434B2Jul 9, 2013
Index generation for cache memories
CAPRIOLI PAUL5 citations73
US10387324B2Aug 20, 2019
Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution
CAPRIOLI PAUL2 citations72
US9652234B2May 16, 2017
Instruction and logic to control transfer in a partial binary translation system
CAPRIOLI PAUL2 citations71
US9542191B2Jan 10, 2017
Hardware profiling mechanism to enable page level automatic binary translation
CAPRIOLI PAUL3 citations69
US9146744B2Sep 29, 2015
Store queue having restricted and unrestricted entries
CAPRIOLI PAUL3 citations62
US11048516B2Jun 29, 2021
Systems, methods, and apparatuses for last branch record support compatible with binary translation and speculative execution using an architectural bit array and a write bit array
CAPRIOLI PAUL0 citations61
US8185692B2May 22, 2012
Unified cache structure that facilitates accessing translation table entries
CAPRIOLI PAUL1 citations52