Assignee
CAVIUM LLC
US113 patents
Top patents by PatentIndex Score
US12112174B2Oct 8, 2024
Streaming engine for machine learning architecture
CAVIUM LLC38 citations97
US10896045B2Jan 19, 2021
Architecture for dense operations in machine learning inference engine
CAVIUM LLC37 citations97
US10282299B2May 7, 2019
Managing cache partitions based on cache usage information
CAVIUM LLC11 citations84
US10558573B1Feb 11, 2020
Methods and systems for distributing memory requests
CAVIUM LLC6 citations83
US10418125B1Sep 17, 2019
Write and read common leveling for 4-bit wide DRAMs
CAVIUM LLC8 citations82
US10878060B2Dec 29, 2020
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor
CAVIUM LLC1 citations73
US10838719B2Nov 17, 2020
Carry chain for SIMD operations
CAVIUM LLC2 citations73
US10772153B2Sep 8, 2020
Methods and apparatus for two-stage ACK/DTX detection
CAVIUM LLC2 citations73
US10684825B2Jun 16, 2020
Compressing like magnitude partial products in multiply accumulation
CAVIUM LLC4 citations73
US10460250B2Oct 29, 2019
Scope in decision trees
CAVIUM LLC4 citations73
US10235211B2Mar 19, 2019
Method and apparatus for dynamic virtual system on chip
CAVIUM LLC4 citations73
US10222817B1Mar 5, 2019
Method and circuit for low voltage current-mode bandgap
CAVIUM LLC3 citations73
US10210135B2Feb 19, 2019
Methods and apparatus for providing a programmable mixed-radix DFT/IDFT processor using vector engines
CAVIUM LLC1 citations73
US10152102B2Dec 11, 2018
Method and apparatus for managing global chip power on a multicore system on chip
CAVIUM LLC3 citations73
US10862617B2Dec 8, 2020
Flowlet scheduler for multicore network processors
CAVIUM LLC2 citations72
US10824433B2Nov 3, 2020
Array-based inference engine for machine learning
CAVIUM LLC2 citations72
US10798108B2Oct 6, 2020
Apparatus and method for a multi-entity secure software transfer
CAVIUM LLC2 citations72
US10331500B2Jun 25, 2019
Managing fairness for lock and unlock operations using operation prioritization
CAVIUM LLC4 citations72
US10263759B2Apr 16, 2019
Signal presence detection circuit and method
CAVIUM LLC3 citations72
US10248420B2Apr 2, 2019
Managing lock and unlock operations using active spinning
CAVIUM LLC2 citations72
US10223279B2Mar 5, 2019
Managing virtual-address caches for multiple memory page sizes
CAVIUM LLC3 citations72
US10146463B2Dec 4, 2018
Method and apparatus for a virtual system on chip
CAVIUM LLC3 citations72
US11119929B2Sep 14, 2021
Low latency inter-chip communication mechanism in multi-chip processing system
CAVIUM LLC2 citations71
US10496329B2Dec 3, 2019
Methods and apparatus for a unified baseband architecture
CAVIUM LLC2 citations71
US10497413B1Dec 3, 2019
Write and read common leveling for 4-bit wide drams
CAVIUM LLC5 citations71
US10461917B2Oct 29, 2019
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
CAVIUM LLC2 citations71
US10409911B2Sep 10, 2019
Systems and methods for text analytics processor
CAVIUM LLC3 citations71
US10404623B2Sep 3, 2019
Multiple ethernet ports and port types using a shared data path
CAVIUM LLC2 citations71
US10291386B2May 14, 2019
Serializer/deserializer (SerDes) lanes with lane-by-lane datarate independence
CAVIUM LLC1 citations71
US11061724B2Jul 13, 2021
Programmable hardware scheduler for digital processing systems
CAVIUM LLC4 citations69
US10599577B2Mar 24, 2020
Admission control for memory access requests
CAVIUM LLC2 citations69
US10592452B1Mar 17, 2020
Low latency interconnect protocol for coherent multi-chip communication
CAVIUM LLC3 citations69
US11113101B2Sep 7, 2021
Method and apparatus for scheduling arbitration among a plurality of service requestors
CAVIUM LLC2 citations68
US10996738B2May 4, 2021
System and method for compensating for a droop event
CAVIUM LLC5 citations68
US10901018B2Jan 26, 2021
System and method for droop detection
CAVIUM LLC5 citations68
US10394730B2Aug 27, 2019
Distributed interrupt scheme in a multi-processor system
CAVIUM LLC2 citations68
US10530826B2Jan 7, 2020
Method and apparatus for providing a low latency transmission system using adjustable buffers
CAVIUM LLC4 citations67
US10303514B2May 28, 2019
Sharing resources in a multi-context computing system
CAVIUM LLC2 citations67
US10389481B2Aug 20, 2019
Methods and apparatus for calculating transport block (TB) cyclic redundancy ceck (CRC) values
CAVIUM LLC6 citations66
US10721172B2Jul 21, 2020
Limiting backpressure with bad actors
CAVIUM LLC2 citations65
US10141949B1Nov 27, 2018
Modular serializer and deserializer
CAVIUM LLC5 citations65
US10250571B2Apr 2, 2019
Systems and methods for offloading IPSEC processing to an embedded networking device
CAVIUM LLC2 citations64
US11297012B2Apr 5, 2022
Packet processing system, method and device having reduced static power consumption
CAVIUM LLC0 citations63
US10977176B2Apr 13, 2021
Prefetching data to reduce cache misses
CAVIUM LLC0 citations63
US10229144B2Mar 12, 2019
NSP manager
CAVIUM LLC1 citations63
US10169080B2Jan 1, 2019
Method for work scheduling in a multi-chip system
CAVIUM LLC1 citations63
US11829322B2Nov 28, 2023
Methods and apparatus for a vector memory subsystem for use with a programmable mixed-radix DFT/IDFT processor
CAVIUM LLC0 citations62
US11700104B2Jul 11, 2023
Methods and apparatus for dynamic acknowledgement list selection in detection of uplink control channel formats
CAVIUM LLC0 citations62
US11314516B2Apr 26, 2022
Issuing instructions based on resource conflict constraints in microprocessor
CAVIUM LLC0 citations62
US11258886B2Feb 22, 2022
Method of handling large protocol layers for configurable extraction of layer information and an apparatus thereof
CAVIUM LLC0 citations62
Showing the top 50 of 113 patents by PatentIndex Score.