Assignee
CHANG HSIEN CHENG
TW·2 granted patents·2 citations·filing 2010–2012
Top patents by PatentIndex Score
2 records- 0162US8723776B2Gate driving circuit receiving a plurality of clock signals and having forward and reverse driving modes and driving method thereofCHANG HSIEN CHENG·Filed 2012·Granted May 13, 2014·1 cites·9 claims
- 0261US8300002B2Gate drive circuit having at least three clock signals and having forward and reverse driving modes and driving method thereofCHANG HSIEN CHENG·Filed 2010·Granted Oct 30, 2012·1 cites·10 claims
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