Assignee

CHENG KANGGUO

US137 patents

Top patents by PatentIndex Score

US8420459B1Apr 16, 2013

Bulk fin-field effect transistors with well defined isolation

CHENG KANGGUO67 citations98

US8546209B1Oct 1, 2013

Replacement metal gate processing with reduced interlevel dielectric layer etch rate

CHENG KANGGUO35 citations94

US8110862B2Feb 7, 2012

Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation

CHENG KANGGUO33 citations93

US8138543B2Mar 20, 2012

Hybrid FinFET/planar SOI FETs

CHENG KANGGUO21 citations93

US8105901B2Jan 31, 2012

Method for double pattern density

CHENG KANGGUO37 citations93

US8084309B2Dec 27, 2011

Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask

CHENG KANGGUO23 citations93

US8395217B1Mar 12, 2013

Isolation in CMOSFET devices utilizing buried air bags

CHENG KANGGUO33 citations92

US8309447B2Nov 13, 2012

Method for integrating multiple threshold voltage devices for CMOS

CHENG KANGGUO21 citations92

US9105577B2Aug 11, 2015

MOSFET with work function adjusted metal backgate

CHENG KANGGUO9 citations84

US9087741B2Jul 21, 2015

CMOS with dual raised source and drain for NMOS and PMOS

CHENG KANGGUO11 citations84

US9048339B2Jun 2, 2015

Deep trench capacitor

CHENG KANGGUO9 citations84

US9034703B2May 19, 2015

Self aligned contact with improved robustness

CHENG KANGGUO13 citations84

US8962423B2Feb 24, 2015

Multilayer MIM capacitor

CHENG KANGGUO8 citations84

US8932918B2Jan 13, 2015

FinFET with self-aligned punchthrough stopper

CHENG KANGGUO17 citations84

US8916933B2Dec 23, 2014

Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure

CHENG KANGGUO5 citations84

US8890245B2Nov 18, 2014

Raised source/drain structure for enhanced strain coupling from stress liner

CHENG KANGGUO7 citations84

US8889564B2Nov 18, 2014

Suspended nanowire structure

CHENG KANGGUO8 citations84

US8853781B2Oct 7, 2014

Rare-earth oxide isolated semiconductor fin

CHENG KANGGUO10 citations84

US8816436B2Aug 26, 2014

Method and structure for forming fin resistors

CHENG KANGGUO16 citations84

US8803233B2Aug 12, 2014

Junctionless transistor

CHENG KANGGUO17 citations84

US8748258B2Jun 10, 2014

Method and structure for forming on-chip high quality capacitors with ETSOI transistors

CHENG KANGGUO15 citations84

US8741701B2Jun 3, 2014

Fin structure formation including partial spacer removal

CHENG KANGGUO15 citations84

US8709890B2Apr 29, 2014

Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts

CHENG KANGGUO19 citations84

US8691650B2Apr 8, 2014

MOSFET with recessed channel film and abrupt junctions

CHENG KANGGUO8 citations84

US8673708B2Mar 18, 2014

Replacement gate ETSOI with sharp junction

CHENG KANGGUO8 citations84

US8652898B2Feb 18, 2014

Integrated circuit with a thin body field effect transistor and capacitor

CHENG KANGGUO5 citations84

US8629506B2Jan 14, 2014

Replacement gate CMOS

CHENG KANGGUO6 citations84

US8617968B1Dec 31, 2013

Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs)

CHENG KANGGUO18 citations84

US8617937B2Dec 31, 2013

Forming narrow fins for finFET devices using asymmetrically spaced mandrels

CHENG KANGGUO11 citations84

US8574970B2Nov 5, 2013

Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain

CHENG KANGGUO16 citations84

US8569159B2Oct 29, 2013

CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication

CHENG KANGGUO13 citations84

US8536032B2Sep 17, 2013

Formation of embedded stressor through ion implantation

CHENG KANGGUO7 citations84

US8525186B2Sep 3, 2013

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

CHENG KANGGUO9 citations84

US8525235B2Sep 3, 2013

Multiplying pattern density by single sidewall imaging transfer

CHENG KANGGUO6 citations84

Showing the top 50 of 137 patents by PatentIndex Score.

CHENG KANGGUO

Top patents by PatentIndex Score

Bulk fin-field effect transistors with well defined isolation

Replacement metal gate processing with reduced interlevel dielectric layer etch rate

Semiconductor structure including trench capacitor and trench resistor

Three dimensional FET devices having different device widths

Bulk finFET with uniform height and bottom isolation

Asymmetric multi-gated transistor and method for forming

Integrated circuit including DRAM and SRAM/logic

Bulk fin-field effect transistors with well defined isolation

MOS capacitors with a finfet process

Borderless contacts for semiconductor devices

CMOS structure having multiple threshold voltage devices

SOI device with DTI and STI

FinFET fuse with enhanced current crowding

Stressed Fin-FET devices with low contact resistance

Raised source/drain structure for enhanced strain coupling from stress liner

Asymmetric FinFET devices

CMOS circuit with low-k spacer and stress liner

Stressed Fin-FET devices with low contact resistance

Method of forming extremely thin semiconductor on insulator (ETSOI) device without ion implantation

Hybrid FinFET/planar SOI FETs

Method for double pattern density

Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask

Isolation in CMOSFET devices utilizing buried air bags

Method for integrating multiple threshold voltage devices for CMOS

MOSFET with work function adjusted metal backgate

CMOS with dual raised source and drain for NMOS and PMOS

Deep trench capacitor

Self aligned contact with improved robustness

Multilayer MIM capacitor

FinFET with self-aligned punchthrough stopper

Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure

Raised source/drain structure for enhanced strain coupling from stress liner

Suspended nanowire structure

Rare-earth oxide isolated semiconductor fin

Method and structure for forming fin resistors

Junctionless transistor

Method and structure for forming on-chip high quality capacitors with ETSOI transistors

Fin structure formation including partial spacer removal

Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts

MOSFET with recessed channel film and abrupt junctions

Replacement gate ETSOI with sharp junction

Integrated circuit with a thin body field effect transistor and capacitor

Replacement gate CMOS

Strained silicon and strained silicon germanium on insulator metal oxide semiconductor field effect transistors (MOSFETs)

Forming narrow fins for finFET devices using asymmetrically spaced mandrels

Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain

CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication

Formation of embedded stressor through ion implantation

Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

Multiplying pattern density by single sidewall imaging transfer