Assignee
CHIOU WEN-CHIH
TW·10 granted patents·1 pending application·79 citations·filing 2007–2012
Top patents by PatentIndex Score
11 records- 0195US8264077B2Backside metal of redistribution line with silicide layer on through-silicon via of semiconductor chipsCHIOU WEN-CHIH·Filed 2008·Granted Sep 11, 2012·36 cites·16 claims
- 0289US9209157B2Formation of through via before contact processingCHIOU WEN-CHIH·Filed 2011·Granted Dec 8, 2015·8 cites·18 claims
- 0389US8252665B2Protection layer for adhesive material at wafer edgeCHIOU WEN-CHIH·Filed 2010·Granted Aug 28, 2012·8 cites·20 claims
- 0488US8441136B2Protection layer for adhesive material at wafer edgeCHIOU WEN-CHIH·Filed 2012·Granted May 14, 2013·7 cites·14 claims
- 0583US8486823B2Methods of forming through viaCHIOU WEN-CHIH·Filed 2008·Granted Jul 16, 2013·10 cites·9 claims
- 0680US8134235B2Three-dimensional semiconductor deviceCHIOU WEN-CHIH·Filed 2007·Granted Mar 13, 2012·5 cites·18 claims
- 0770US8587127B2Semiconductor structures and methods of forming the sameCHIOU WEN-CHIH·Filed 2011·Granted Nov 19, 2013·2 cites·20 claims
- 0863US9390949B2Wafer debonding and cleaning apparatus and method of useCHIOU WEN-CHIH·Filed 2011·Granted Jul 12, 2016·1 cites·20 claims
- 0962US8647925B2Surface modification for handling wafer thinning processCHIOU WEN-CHIH·Filed 2010·Granted Feb 11, 2014·2 cites·20 claims
- 1054US9130024B2Three-dimensional semiconductor deviceCHIOU WEN-CHIH·Filed 2012·Granted Sep 8, 2015·0 cites·18 claims
- 1147US2009273002A1LED Package Structure and Fabrication MethodCHIOU WEN-CHIH·Filed 2008·Application pending·0 cites
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