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CHIPMOS TECHNOLOGIES INC
TW123 patents
Top patents by PatentIndex Score
US7662667B2Feb 16, 2010
Die rearrangement package structure using layout process to form a compliant configuration
CHIPMOS TECHNOLOGIES INC63 citations98
US6534853B2Mar 18, 2003
Semiconductor wafer designed to avoid probed marks while testing
CHIPMOS TECHNOLOGIES INC141 citations97
US7642137B2Jan 5, 2010
Manufacturing method of chip package
CHIPMOS TECHNOLOGIES INC83 citations96
US7088118B2Aug 8, 2006
Modularized probe card for high frequency probing
CHIPMOS TECHNOLOGIES INC55 citations95
US6946860B2Sep 20, 2005
Modularized probe head
CHIPMOS TECHNOLOGIES INC57 citations95
US7927922B2Apr 19, 2011
Dice rearrangement package structure using layout process to form a compliant configuration
CHIPMOS TECHNOLOGIES INC30 citations92
US7915690B2Mar 29, 2011
Die rearrangement package structure using layout process to form a compliant configuration
CHIPMOS TECHNOLOGIES INC26 citations92
US7663246B2Feb 16, 2010
Stacked chip packaging with heat sink structure
CHIPMOS TECHNOLOGIES INC22 citations92
US7615853B2Nov 10, 2009
Chip-stacked package structure having leadframe with multi-piece bus bar
CHIPMOS TECHNOLOGIES INC21 citations92
US7129730B2Oct 31, 2006
Probe card assembly
CHIPMOS TECHNOLOGIES INC35 citations92
US7932531B2Apr 26, 2011
Chip package
CHIPMOS TECHNOLOGIES INC29 citations91
US7723853B2May 25, 2010
Chip package without core and stacked chip package structure
CHIPMOS TECHNOLOGIES INC17 citations91
US7436074B2Oct 14, 2008
Chip package without core and stacked chip package structure thereof
CHIPMOS TECHNOLOGIES INC34 citations91
US7510889B2Mar 31, 2009
Light emitting chip package and manufacturing method thereof
CHIPMOS TECHNOLOGIES INC32 citations90
US6034425AMar 7, 2000
Flat multiple-chip module micro ball grid array packaging
CHIPMOS TECHNOLOGIES INC26 citations90
US6023097AFeb 8, 2000
Stacked multiple-chip module micro ball grid array packaging
CHIPMOS TECHNOLOGIES INC24 citations90
US7973310B2Jul 5, 2011
Semiconductor package structure and method for manufacturing the same
CHIPMOS TECHNOLOGIES INC37 citations89
US9728479B2Aug 8, 2017
Multi-chip package structure, wafer level chip package structure and manufacturing process thereof
CHIPMOS TECHNOLOGIES INC9 citations84
US7781878B2Aug 24, 2010
Zigzag-stacked package structure
CHIPMOS TECHNOLOGIES INC16 citations84
US7528495B2May 5, 2009
Chip structure
CHIPMOS TECHNOLOGIES INC9 citations84
US8836144B2Sep 16, 2014
Wafer level package structure
CHIPMOS TECHNOLOGIES INC5 citations83
US7816771B2Oct 19, 2010
Stacked chip package structure with leadframe having inner leads with transfer pad
CHIPMOS TECHNOLOGIES INC14 citations83
US6395622B1May 28, 2002
Manufacturing process of semiconductor devices
CHIPMOS TECHNOLOGIES INC16 citations83
US7582953B2Sep 1, 2009
Package structure with leadframe on offset chip-stacked structure
CHIPMOS TECHNOLOGIES INC16 citations82
US8779604B1Jul 15, 2014
Semiconductor structure and manufacturing method thereof
CHIPMOS TECHNOLOGIES INC9 citations81
US7969003B2Jun 28, 2011
Bump structure having a reinforcement member
CHIPMOS TECHNOLOGIES INC11 citations81
US7888172B2Feb 15, 2011
Chip stacked structure and the forming method
CHIPMOS TECHNOLOGIES INC15 citations81
US7609053B2Oct 27, 2009
Wafer testing system integrated with RFID techniques and thesting method thereof
CHIPMOS TECHNOLOGIES INC8 citations77
US7915730B2Mar 29, 2011
Packaging conductive structure and method for manufacturing the same
CHIPMOS TECHNOLOGIES INC7 citations75
US7812432B2Oct 12, 2010
Chip package with a dam structure on a die pad
CHIPMOS TECHNOLOGIES INC13 citations75
US10002815B2Jun 19, 2018
Multi-chip package structure manufacturing process and wafer level chip package structure manufacturing process
CHIPMOS TECHNOLOGIES INC2 citations73
US9653429B2May 16, 2017
Multi-chip package structure having blocking structure, wafer level chip package structure having blocking structure and manufacturing process thereof
CHIPMOS TECHNOLOGIES INC2 citations73
US7786595B2Aug 31, 2010
Stacked chip package structure with leadframe having bus bar
CHIPMOS TECHNOLOGIES INC7 citations73
US7576416B2Aug 18, 2009
Chip package having with asymmetric molding and turbulent plate downset design
CHIPMOS TECHNOLOGIES INC7 citations73
US9269643B2Feb 23, 2016
Chip package structure
CHIPMOS TECHNOLOGIES INC4 citations72
US8877630B1Nov 4, 2014
Semiconductor structure having a silver alloy bump body and manufacturing method thereof
CHIPMOS TECHNOLOGIES INC5 citations70
US7651886B2Jan 26, 2010
Semiconductor device and manufacturing process thereof
CHIPMOS TECHNOLOGIES INC7 citations70
US6960491B2Nov 1, 2005
Integrated circuit packaging for improving effective chip-bonding area
CHIPMOS TECHNOLOGIES INC7 citations70
US9780056B1Oct 3, 2017
Solder ball, manufacturing method thereof, and semiconductor device
CHIPMOS TECHNOLOGIES INC3 citations69
US9401318B2Jul 26, 2016
Quad flat no-lead package and manufacturing method thereof
CHIPMOS TECHNOLOGIES INC3 citations66
US9721913B2Aug 1, 2017
Semiconductor package and method of manufacturing thereof
CHIPMOS TECHNOLOGIES INC3 citations65
US8962395B2Feb 24, 2015
QFN package and manufacturing process thereof
CHIPMOS TECHNOLOGIES INC3 citations63
US7981725B2Jul 19, 2011
Fabricating process of a chip package structure
CHIPMOS TECHNOLOGIES INC2 citations63
US7960214B2Jun 14, 2011
Chip package
CHIPMOS TECHNOLOGIES INC2 citations63
US7749806B2Jul 6, 2010
Fabricating process of a chip package structure
CHIPMOS TECHNOLOGIES INC3 citations63
US7700412B2Apr 20, 2010
Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers
CHIPMOS TECHNOLOGIES INC5 citations63
US7638880B2Dec 29, 2009
Chip package
CHIPMOS TECHNOLOGIES INC2 citations63
US7560306B2Jul 14, 2009
Manufacturing process for chip package without core
CHIPMOS TECHNOLOGIES INC3 citations63
US7538419B2May 26, 2009
Stacked-type chip package structure
CHIPMOS TECHNOLOGIES INC2 citations63
US7504714B2Mar 17, 2009
Chip package with asymmetric molding
CHIPMOS TECHNOLOGIES INC2 citations63
Showing the top 50 of 123 patents by PatentIndex Score.