Assignee
CHLIPALA JAMES D
US·2 granted patents·1 pending application·4 citations·filing 2006–2008
Top patents by PatentIndex Score
3 records- 0155US8680907B2Delay circuit having reduced duty cycle distortionCHLIPALA JAMES D·Filed 2008·Granted Mar 25, 2014·3 cites·23 claims
- 0251US8180600B2Input/output buffer information specification (IBIS) model generation for multi-chip modules (MCM) and similar devicesCHLIPALA JAMES D·Filed 2006·Granted May 15, 2012·1 cites·23 claims
- 0333US2008129357A1Adaptive Integrated Circuit Clock Skew CorrectionCHLIPALA JAMES D·Filed 2006·Application pending·0 cites
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