Assignee
CHOI DAESIK
KR·25 granted patents·3 pending applications·492 citations·filing 2008–2013
Top patents by PatentIndex Score
28 records- 0198US8895440B2Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMVCHOI DAESIK·Filed 2010·Granted Nov 25, 2014·81 cites·23 claims
- 0298US8476115B2Semiconductor device and method of mounting cover to semiconductor die and interposer with adhesive materialCHOI DAESIK·Filed 2011·Granted Jul 2, 2013·47 cites·32 claims
- 0398US8232141B2Integrated circuit packaging system with conductive pillars and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Jul 31, 2012·114 cites·11 claims
- 0497US8063475B2Semiconductor package system with through silicon via interposerCHOI DAESIK·Filed 2008·Granted Nov 22, 2011·56 cites·18 claims
- 0596US8502387B2Integrated circuit packaging system with vertical interconnection and method of manufacture thereofCHOI DAESIK·Filed 2010·Granted Aug 6, 2013·48 cites·20 claims
- 0696US8263435B2Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive viasCHOI DAESIK·Filed 2010·Granted Sep 11, 2012·47 cites·25 claims
- 0795US8409979B2Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection propertiesCHOI DAESIK·Filed 2011·Granted Apr 2, 2013·17 cites·17 claims
- 0890US9190297B2Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structuresCHOI DAESIK·Filed 2011·Granted Nov 17, 2015·14 cites·36 claims
- 0989US8648469B2Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrateCHOI DAESIK·Filed 2011·Granted Feb 11, 2014·8 cites·26 claims
- 1088US9252094B2Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillarCHOI DAESIK·Filed 2011·Granted Feb 2, 2016·10 cites·17 claims
- 1186US8466567B2Integrated circuit packaging system with stack interconnect and method of manufacture thereofCHOI DAESIK·Filed 2010·Granted Jun 18, 2013·9 cites·14 claims
- 1284US9312218B2Semiconductor device and method of forming leadframe with conductive bodies for vertical electrical interconnect of semiconductor dieCHOI DAESIK·Filed 2011·Granted Apr 12, 2016·8 cites·20 claims
- 1383US9281228B2Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor dieCHOI DAESIK·Filed 2011·Granted Mar 8, 2016·7 cites·32 claims
- 1483US9252032B2Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive viasCHOI DAESIK·Filed 2012·Granted Feb 2, 2016·6 cites·31 claims
- 1579US8679900B2Integrated circuit packaging system with heat conduction and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Mar 25, 2014·6 cites·2 claims
- 1678US8710640B2Integrated circuit packaging system with heat slug and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Apr 29, 2014·5 cites·18 claims
- 1777US9406579B2Semiconductor device and method of controlling warpage in semiconductor packageCHOI DAESIK·Filed 2012·Granted Aug 2, 2016·5 cites·27 claims
- 1866US8642469B2Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor waferCHOI DAESIK·Filed 2011·Granted Feb 4, 2014·2 cites·31 claims
- 1959US8067307B2Integrated circuit package system for stackable devicesCHOI DAESIK·Filed 2008·Granted Nov 29, 2011·1 cites·20 claims
- 2055US8748233B2Integrated circuit packaging system with underfill and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Jun 10, 2014·1 cites·5 claims
- 2153US9082887B1Integrated circuit packaging system with posts and method of manufacture thereofCHOI DAESIK·Filed 2013·Granted Jul 14, 2015·0 cites·20 claims
- 2248US8703538B2Integrated circuit packaging system with external wire connection and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Apr 22, 2014·0 cites·10 claims
- 2347US2012273937A1Semiconductor Device and Method of Forming Bump Interconnect Structure with Conductive Layer Over Buffer LayerCHOI DAESIK·Filed 2011·Application pending·0 cites
- 2444US8994192B2Integrated circuit packaging system with perimeter antiwarpage structure and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Mar 31, 2015·0 cites·10 claims
- 2544US2011291264A1Integrated circuit packaging system with posts and method of manufacture thereofCHOI DAESIK·Filed 2010·Application pending·0 cites
- 2643US9059108B2Integrated circuit packaging system with interconnectsCHOI DAESIK·Filed 2012·Granted Jun 16, 2015·0 cites·10 claims
- 2743US8633058B2Integrated circuit packaging system with step mold and method of manufacture thereofCHOI DAESIK·Filed 2011·Granted Jan 21, 2014·0 cites·11 claims
- 2837US2013049188A1Semiconductor Device and Method of Forming TIM Within Recesses of MUF MaterialCHOI DAESIK·Filed 2011·Application pending·0 cites
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →