Assignee
CHOI JOONYOUNG
KR·4 granted patents·15 citations·filing 2010–2013
Top patents by PatentIndex Score
4 records- 0180US8835301B2Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor waferCHOI JOONYOUNG·Filed 2011·Granted Sep 16, 2014·5 cites·25 claims
- 0279US8546194B2Integrated circuit packaging system with interconnects and method of manufacture thereofCHOI JOONYOUNG·Filed 2011·Granted Oct 1, 2013·6 cites·20 claims
- 0373US8994048B2Semiconductor device and method of forming recesses in substrate for same size or different sized die with vertical integrationCHOI JOONYOUNG·Filed 2010·Granted Mar 31, 2015·4 cites·29 claims
- 0447US9093278B1Method of manufacture of integrated circuit packaging system with plasma processingCHOI JOONYOUNG·Filed 2013·Granted Jul 28, 2015·0 cites·20 claims
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