Assignee
CHOI SEOK-WOO
KR·2 granted patents·21 citations·filing 2010–2010
Top patents by PatentIndex Score
2 records- 0186US8411517B2Delay locked loop circuit including delay line with reduced sensitivity to variation in PVTCHOI SEOK-WOO·Filed 2010·Granted Apr 2, 2013·15 cites·19 claims
- 0278US8149015B2Transceiver system, semiconductor device thereof, and data transceiving method of the sameCHOI SEOK-WOO·Filed 2010·Granted Apr 3, 2012·6 cites·21 claims
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