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CYRIX CORP

US82 patents

Top patents by PatentIndex Score

US5630149AMay 13, 1997

Pipelined processor with register renaming hardware to accommodate multiple size registers

CYRIX CORP125 citations98

US5233314AAug 3, 1993

Integrated charge-pump phase-locked loop circuit

CYRIX CORP183 citations98

US5734881AMar 31, 1998

Detecting short branches in a prefetch buffer using target location information in a branch target cache

CYRIX CORP133 citations97

US5471598ANov 28, 1995

Data dependency detection and handling in a microprocessor with write buffer

CYRIX CORP139 citations97

US5835967ANov 10, 1998

Adjusting prefetch size based on source of prefetch address

CYRIX CORP89 citations96

US5706491AJan 6, 1998

Branch processing unit with a return stack including repair using pointers from different pipe stages

CYRIX CORP91 citations96

US5692168ANov 25, 1997

Prefetch buffer using flow control bit to identify changes of flow within the code stream

CYRIX CORP83 citations96

US5687202ANov 11, 1997

Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception

CYRIX CORP74 citations96

US5524234AJun 4, 1996

Coherency for write-back cache in a system designed for write-through cache including write-back latency control

CYRIX CORP60 citations95

US5359232AOct 25, 1994

Clock multiplication circuit and method

CYRIX CORP85 citations95

US5336939AAug 9, 1994

Stable internal clock generation for an integrated circuit

CYRIX CORP88 citations95

US5724549AMar 3, 1998

Cache coherency without bus master arbitration signals

CYRIX CORP100 citations94

US5644788AJul 1, 1997

Burst transfers using an ascending or descending only burst ordering

CYRIX CORP86 citations94

US5379240AJan 3, 1995

Shifter/rotator with preconditioned data

CYRIX CORP67 citations94

US5838897ANov 17, 1998

Debugging a processor using data output during idle bus cycles

CYRIX CORP40 citations92

US5805879ASep 8, 1998

In a pipelined processor, setting a segment access indicator during execution stage using exception handling

CYRIX CORP56 citations92

US5784589AJul 21, 1998

Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline

CYRIX CORP29 citations92

US5777500AJul 7, 1998

Multiple clock source generation with independently adjustable duty cycles

CYRIX CORP37 citations92

US5771365AJun 23, 1998

Condensed microaddress generation in a complex instruction set computer

CYRIX CORP24 citations92

US5740416AApr 14, 1998

Branch processing unit with a far target cache accessed by indirection from the target cache

CYRIX CORP24 citations92

US5740398AApr 14, 1998

Program order sequencing of data in a microprocessor with write buffer

CYRIX CORP49 citations92

US5740410AApr 14, 1998

Static clock generator

CYRIX CORP26 citations92

US5732253AMar 24, 1998

Branch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branches

CYRIX CORP31 citations92

US5732243AMar 24, 1998

Branch processing unit with target cache using low/high banking to support split prefetching

CYRIX CORP40 citations92

US5615402AMar 25, 1997

Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch

CYRIX CORP27 citations92

US5596740AJan 21, 1997

Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks

CYRIX CORP50 citations92

US5596735AJan 21, 1997

Circuit and method for addressing segment descriptor tables

CYRIX CORP28 citations92

US5592107AJan 7, 1997

Configurable NAND/NOR element

CYRIX CORP21 citations92

US5568067AOct 22, 1996

Configurable XNOR/XOR element

CYRIX CORP23 citations92

US5524222AJun 4, 1996

Microsequencer allowing a sequence of conditional jumps without requiring the insertion of NOP or other instructions

CYRIX CORP28 citations92

US5307303AApr 26, 1994

Method and apparatus for performing division using a rectangular aspect ratio multiplier

CYRIX CORP53 citations92

US5060182AOct 22, 1991

Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier

CYRIX CORP32 citations92

US5046038ASep 3, 1991

Method and apparatus for performing division using a rectangular aspect ratio multiplier

CYRIX CORP68 citations92

US5764999AJun 9, 1998

Enhanced system management mode with nesting

CYRIX CORP92 citations91

US5701448ADec 23, 1997

Detecting segment limit violations for branch target when the branch unit does not supply the linear address

CYRIX CORP45 citations91

US5664149ASep 2, 1997

Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol

CYRIX CORP30 citations91

US5611071AMar 11, 1997

Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture

CYRIX CORP42 citations91

US5410671AApr 25, 1995

Data compression/decompression processor

CYRIX CORP156 citations91

US5337269AAug 9, 1994

Carry skip adder with independent carry-in and carry skip paths

CYRIX CORP24 citations91

US5042001AAug 20, 1991

Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier

CYRIX CORP63 citations91

US5040138AAug 13, 1991

Circuit for simultaneous arithmetic calculation and normalization estimation

CYRIX CORP30 citations91

US5752274AMay 12, 1998

Address translation unit employing a victim TLB

CYRIX CORP54 citations90

US5428622AJun 27, 1995

Testing architecture with independent scan paths

CYRIX CORP70 citations90

US5420989AMay 30, 1995

Coprocessor interface supporting I/O or memory mapped communications

CYRIX CORP37 citations87

Showing the top 50 of 82 patents by PatentIndex Score.

CYRIX CORP

Top patents by PatentIndex Score

Pipelined processor with register renaming hardware to accommodate multiple size registers

Integrated charge-pump phase-locked loop circuit

Detecting short branches in a prefetch buffer using target location information in a branch target cache

Data dependency detection and handling in a microprocessor with write buffer

Adjusting prefetch size based on source of prefetch address

Branch processing unit with a return stack including repair using pointers from different pipe stages

Prefetch buffer using flow control bit to identify changes of flow within the code stream

Programmable phase shift clock generator

Adjustable duty cycle clock generator

Microprocessor having power management circuitry with coprocessor support

Microprocessor with externally controllable power management

System and method of retiring store data from a write buffer

Single delay line adjustable duty cycle clock generator

Exception handling for prefetched instruction bytes using valid bits to identify instructions that will cause an exception

Coherency for write-back cache in a system designed for write-through cache including write-back latency control

Clock multiplication circuit and method

Stable internal clock generation for an integrated circuit

Cache coherency without bus master arbitration signals

Burst transfers using an ascending or descending only burst ordering

Shifter/rotator with preconditioned data

Debugging a processor using data output during idle bus cycles

In a pipelined processor, setting a segment access indicator during execution stage using exception handling

Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline

Multiple clock source generation with independently adjustable duty cycles

Condensed microaddress generation in a complex instruction set computer

Branch processing unit with a far target cache accessed by indirection from the target cache

Program order sequencing of data in a microprocessor with write buffer

Static clock generator

Branch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branches

Branch processing unit with target cache using low/high banking to support split prefetching

Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch

Interleaved memory conflict resolution with accesses of variable bank widths and partial return of non-conflicting banks

Circuit and method for addressing segment descriptor tables

Configurable NAND/NOR element

Configurable XNOR/XOR element

Microsequencer allowing a sequence of conditional jumps without requiring the insertion of NOP or other instructions

Method and apparatus for performing division using a rectangular aspect ratio multiplier

Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier

Method and apparatus for performing division using a rectangular aspect ratio multiplier

Enhanced system management mode with nesting

Detecting segment limit violations for branch target when the branch unit does not supply the linear address

Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol

Split replacement cycles for sectored cache lines in a 64-bit microprocessor interfaced to a 32-bit bus architecture

Data compression/decompression processor

Carry skip adder with independent carry-in and carry skip paths

Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier

Circuit for simultaneous arithmetic calculation and normalization estimation

Address translation unit employing a victim TLB

Testing architecture with independent scan paths

Coprocessor interface supporting I/O or memory mapped communications