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ESILICON CORP
US27 patents
Top patents by PatentIndex Score
US7218980B1May 15, 2007
Prediction based optimization of a semiconductor supply chain using an adaptive real time work-in-progress tracking system
ESILICON CORP61 citations93
US6748287B1Jun 8, 2004
Adaptive real-time work-in-progress tracking, prediction, and optimization system for a semiconductor supply chain
ESILICON CORP100 citations93
US10469096B1Nov 5, 2019
Successive approximation register (SAR) analog to digital converter (ADC) with partial loop-unrolling
ESILICON CORP7 citations81
US8355269B1Jan 15, 2013
Pushed-rule bit cells with new functionality
ESILICON CORP13 citations81
US9762261B2Sep 12, 2017
Error detection and correction in ternary content addressable memory (TCAM)
ESILICON CORP8 citations80
US9454636B1Sep 27, 2016
Integrated circuit design optimization
ESILICON CORP4 citations80
US10050003B2Aug 14, 2018
Elongated pad structure
ESILICON CORP2 citations73
US10554449B1Feb 4, 2020
Baseline wander compensation in SerDes transceivers
ESILICON CORP3 citations71
US10454491B1Oct 22, 2019
Successive approximation register (SAR) analog to digital converter (ADC) with partial loop-unrolling
ESILICON CORP3 citations70
US10032516B2Jul 24, 2018
Duo content addressable memory (CAM) using a single CAM
ESILICON CORP2 citations67
US9435846B2Sep 6, 2016
Testing of thru-silicon vias
ESILICON CORP2 citations62
US9454628B1Sep 27, 2016
Scaling memory components of integrated circuit design
ESILICON CORP1 citations59
US7474933B2Jan 6, 2009
System and method for automating integration of semiconductor work in process updates
ESILICON CORP7 citations58
US9852250B2Dec 26, 2017
Memory optimization in VLSI design using generic memory models
ESILICON CORP1 citations57
US9727682B2Aug 8, 2017
Designing memories in VLSI design using specific memory models generated from generic memory models
ESILICON CORP1 citations57
US10018670B2Jul 10, 2018
Wireless probes
ESILICON CORP0 citations52
US9984997B2May 29, 2018
Communication interface architecture using serializer/deserializer
ESILICON CORP0 citations52
US9461000B2Oct 4, 2016
Parallel signal via structure
ESILICON CORP1 citations52
US9263409B2Feb 16, 2016
Mixed-sized pillars that are probeable and routable
ESILICON CORP0 citations52
US9529669B2Dec 27, 2016
Error detection and correction in binary content addressable memory (BCAM)
ESILICON CORP0 citations48
US9460254B1Oct 4, 2016
Scaling logic components of integrated circuit design
ESILICON CORP0 citations48
US9460255B1Oct 4, 2016
Scaling of integrated circuit design including logic and memory components
ESILICON CORP0 citations48
US9460257B1Oct 4, 2016
Scaling of integrated circuit design including high-level logic components
ESILICON CORP0 citations48
US9460256B1Oct 4, 2016
Integrated circuit design scaling for recommending design point
ESILICON CORP0 citations48
US9727681B2Aug 8, 2017
Generating specific memory models using generic memory models for designing memories in VLSI design
ESILICON CORP0 citations46
US9711220B2Jul 18, 2017
Duo content addressable memory (CAM) using a single CAM
ESILICON CORP1 citations46
US7756598B2Jul 13, 2010
System and method for automating integration of semiconductor work in process updates
ESILICON CORP1 citations33