Assignee
FULLER NICHOLAS C
US·5 granted patents·3 pending applications·38 citations·filing 2008–2012
Top patents by PatentIndex Score
8 records- 0193US8084825B2Trilayer resist scheme for gate etching applicationsFULLER NICHOLAS C·Filed 2008·Granted Dec 27, 2011·22 cites·14 claims
- 0284US8431995B2Methodology for fabricating isotropically recessed drain regions of CMOS transistorsFULLER NICHOLAS C·Filed 2010·Granted Apr 30, 2013·6 cites·4 claims
- 0380US8716798B2Methodology for fabricating isotropically recessed source and drain regions of CMOS transistorsFULLER NICHOLAS C·Filed 2010·Granted May 6, 2014·4 cites·12 claims
- 0479US9006108B2Methodology for fabricating isotropically recessed source and drain regions of CMOS transistorsFULLER NICHOLAS C·Filed 2012·Granted Apr 14, 2015·4 cites·5 claims
- 0558US8334090B2Mixed lithography with dual resist and a single pattern transferFULLER NICHOLAS C·Filed 2011·Granted Dec 18, 2012·2 cites·10 claims
- 0651US2012305928A1Methodology for fabricating isotropically recessed source regions of cmos transistorsFULLER NICHOLAS C·Filed 2012·Application pending·0 cites
- 0751US2014231809A1Methodology for fabricating isotropically recessed source regions of cmos transistorsFULLER NICHOLAS C·Filed 2012·Application pending·0 cites
- 0847US2011278580A1Methodology for fabricating isotropically source regions of cmos transistorsFULLER NICHOLAS C·Filed 2010·Application pending·0 cites
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