Assignee
GONG YUPING
CN7 patents
Top patents by PatentIndex Score
US8841167B1Sep 23, 2014
Manufacturing method of a semiconductor package of small footprint with a stack of lead frame die paddle sandwiched between high-side and low-side MOSFET
GONG YUPING8 citations83
US8642397B1Feb 4, 2014
Semiconductor wafer level package (WLP) and method of manufacture thereof
GONG YUPING9 citations83
US8519520B2Aug 27, 2013
Semiconductor package of small footprint with a stack of lead frame die paddle sandwich between high-side and low-side MOSFETs and manufacturing method
GONG YUPING8 citations83
US8163601B2Apr 24, 2012
Chip-exposed semiconductor device and its packaging method
GONG YUPING6 citations83
US8236613B2Aug 7, 2012
Wafer level chip scale package method using clip array
GONG YUPING4 citations61
US9006901B2Apr 14, 2015
Thin power device and preparation method thereof
GONG YUPING0 citations51
US8450152B2May 28, 2013
Double-side exposed semiconductor device and its manufacturing method
GONG YUPING0 citations51