Assignee
HENRY G GLENN
US·68 granted patents·1 pending application·324 citations·filing 2002–2012
Top patents by PatentIndex Score
69 records- 0197US8978132B2Apparatus and method for managing a microprocessor providing for a secure execution modeHENRY G GLENN·Filed 2008·Granted Mar 10, 2015·41 cites·24 claims
- 0297US8242800B2Apparatus and method for override access to a secured programmable fuse arrayHENRY G GLENN·Filed 2010·Granted Aug 14, 2012·29 cites·24 claims
- 0393US9043580B2Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)HENRY G GLENN·Filed 2012·Granted May 26, 2015·21 cites·18 claims
- 0493US8615799B2Microprocessor having secure non-volatile storage accessHENRY G GLENN·Filed 2008·Granted Dec 24, 2013·17 cites·22 claims
- 0590US8615672B2Multicore processor power credit management to allow all processing cores to operate at elevated frequencyHENRY G GLENN·Filed 2011·Granted Dec 24, 2013·8 cites·36 claims
- 0690US8392693B2Fast REP STOS using grabline operationsHENRY G GLENN·Filed 2010·Granted Mar 5, 2013·13 cites·34 claims
- 0789US8972707B2Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pinHENRY G GLENN·Filed 2011·Granted Mar 3, 2015·8 cites·12 claims
- 0888US8819839B2Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levelsHENRY G GLENN·Filed 2008·Granted Aug 26, 2014·19 cites·24 claims
- 0988US8793803B2Termination of secure execution mode in a microprocessor providing for execution of secure codeHENRY G GLENN·Filed 2008·Granted Jul 29, 2014·9 cites·27 claims
- 1087US9244686B2Microprocessor that translates conditional load/store instructions into variable number of microinstructionsHENRY G GLENN·Filed 2012·Granted Jan 26, 2016·10 cites·47 claims
- 1186US8533437B2Guaranteed prefetch instructionHENRY G GLENN·Filed 2010·Granted Sep 10, 2013·9 cites·29 claims
- 1285US8276032B2Detection of uncorrectable re-grown fuses in a microprocessorHENRY G GLENN·Filed 2010·Granted Sep 25, 2012·6 cites·21 claims
- 1384US8719589B2Microprocessor that facilitates task switching between multiple encrypted programs having different associated decryption key valuesHENRY G GLENN·Filed 2011·Granted May 6, 2014·4 cites·29 claims
- 1483US8782451B2Power state synchronization in a multi-core processorHENRY G GLENN·Filed 2011·Granted Jul 15, 2014·6 cites·23 claims
- 1581US9317288B2Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipelineHENRY G GLENN·Filed 2012·Granted Apr 19, 2016·6 cites·20 claims
- 1681US9274795B2Conditional non-branch instruction predictionHENRY G GLENN·Filed 2012·Granted Mar 1, 2016·6 cites·22 claims
- 1781US8316243B2Apparatus and method for generating unpredictable processor-unique serial number for use as an encryption keyHENRY G GLENN·Filed 2010·Granted Nov 20, 2012·6 cites·19 claims
- 1880US8341472B2Apparatus and method for tamper protection of a microprocessor fuse arrayHENRY G GLENN·Filed 2010·Granted Dec 25, 2012·4 cites·24 claims
- 1979US8880851B2Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipelineHENRY G GLENN·Filed 2011·Granted Nov 4, 2014·4 cites·22 claims
- 2079US8838924B2Microprocessor having internal secure memoryHENRY G GLENN·Filed 2008·Granted Sep 16, 2014·4 cites·24 claims
- 2179US8209763B2Processor with non-volatile mode enable register entering secure execution mode and encrypting secure program for storage in secure memory via private busHENRY G GLENN·Filed 2008·Granted Jun 26, 2012·4 cites·21 claims
- 2277US8281198B2User-initiatable method for detecting re-grown fuses within a microprocessorHENRY G GLENN·Filed 2010·Granted Oct 2, 2012·3 cites·25 claims
- 2376US8935549B2Microprocessor with multicore processor power credit management featureHENRY G GLENN·Filed 2011·Granted Jan 13, 2015·3 cites·20 claims
- 2476US8914661B2Multicore processor power credit management in which multiple processing cores use shared memory to communicate individual energy consumptionHENRY G GLENN·Filed 2011·Granted Dec 16, 2014·3 cites·34 claims
- 2576US8762687B2Microprocessor providing isolated timers and counters for execution of secure codeHENRY G GLENN·Filed 2008·Granted Jun 24, 2014·3 cites·23 claims
- 2676US8639945B2Branch and switch key instruction in a microprocessor that fetches and decrypts encrypted instructionsHENRY G GLENN·Filed 2011·Granted Jan 28, 2014·2 cites·27 claims
- 2775US9002014B2On-die cryptographic apparatus in a secure microprocessorHENRY G GLENN·Filed 2008·Granted Apr 7, 2015·3 cites·21 claims
- 2875US8631256B2Distributed management of a shared power source to a multi-core microprocessorHENRY G GLENN·Filed 2011·Granted Jan 14, 2014·3 cites·15 claims
- 2974US8930676B2Master core discovering enabled cores in microprocessor comprising plural multi-core diesHENRY G GLENN·Filed 2011·Granted Jan 6, 2015·3 cites·26 claims
- 3074US8521996B2Pipelined microprocessor with fast non-selective correct conditional branch instruction resolutionHENRY G GLENN·Filed 2009·Granted Aug 27, 2013·5 cites·24 claims
- 3174US8464032B2Microprocessor integrated circuit with first processor that outputs debug information in response to reset by second processor of the integrated circuitHENRY G GLENN·Filed 2010·Granted Jun 11, 2013·4 cites·26 claims
- 3274US8069339B2Microprocessor with microinstruction-specifiable non-architectural condition code flag registerHENRY G GLENN·Filed 2009·Granted Nov 29, 2011·6 cites·22 claims
- 3373US9128701B2Generating constant for microinstructions from modified immediate field during instruction translationHENRY G GLENN·Filed 2012·Granted Sep 8, 2015·3 cites·22 claims
- 3473US8635476B2Decentralized power management distributed among multiple processor coresHENRY G GLENN·Filed 2011·Granted Jan 21, 2014·3 cites·20 claims
- 3572US8910276B2Apparatus and method for precluding execution of certain instructions in a secure execution mode microprocessorHENRY G GLENN·Filed 2008·Granted Dec 9, 2014·2 cites·24 claims
- 3672US8607034B2Apparatus and method for disabling a microprocessor that provides for a secure execution modeHENRY G GLENN·Filed 2008·Granted Dec 10, 2013·2 cites·18 claims
- 3772US8522354B2Microprocessor apparatus for secure on-die real-time clockHENRY G GLENN·Filed 2008·Granted Aug 27, 2013·2 cites·25 claims
- 3872US8495344B2Simultaneous execution resumption of multiple processor cores after core state information dump to facilitate debugging via multi-core processor simulator using the state informationHENRY G GLENN·Filed 2010·Granted Jul 23, 2013·4 cites·26 claims
- 3972US8281222B2Detection and correction of fuse re-growth in a microprocessorHENRY G GLENN·Filed 2010·Granted Oct 2, 2012·2 cites·21 claims
- 4071US8645714B2Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructionsHENRY G GLENN·Filed 2011·Granted Feb 4, 2014·1 cites·20 claims
- 4168US9378019B2Conditional load instructions in an out-of-order execution microprocessorHENRY G GLENN·Filed 2012·Granted Jun 28, 2016·2 cites·39 claims
- 4268US9146742B2Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISAHENRY G GLENN·Filed 2012·Granted Sep 29, 2015·2 cites·20 claims
- 4368US8423751B2Microprocessor with fast execution of call and return instructionsHENRY G GLENN·Filed 2009·Granted Apr 16, 2013·3 cites·21 claims
- 4467US9176733B2Load multiple and store multiple instructions in a microprocessor that emulates banked registersHENRY G GLENN·Filed 2012·Granted Nov 3, 2015·2 cites·17 claims
- 4566US8856496B2Microprocessor that fuses load-alu-store and JCC macroinstructionsHENRY G GLENN·Filed 2011·Granted Oct 7, 2014·2 cites·20 claims
- 4664US8402279B2Apparatus and method for updating set of limited access model specific registers in a microprocessorHENRY G GLENN·Filed 2009·Granted Mar 19, 2013·2 cites·29 claims
- 4763US8635437B2Pipelined microprocessor with fast conditional branch instructions based on static exception stateHENRY G GLENN·Filed 2009·Granted Jan 21, 2014·1 cites·28 claims
- 4862US9645822B2Conditional store instructions in an out-of-order execution microprocessorHENRY G GLENN·Filed 2012·Granted May 9, 2017·1 cites·43 claims
- 4962US9032189B2Efficient conditional ALU instruction in read-port limited register file microprocessorHENRY G GLENN·Filed 2011·Granted May 12, 2015·1 cites·34 claims
- 5062US8429471B2Microprocessor apparatus and method for securing a programmable fuse arrayHENRY G GLENN·Filed 2010·Granted Apr 23, 2013·1 cites·21 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
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