Assignee
HO YUEH-SE
US·9 granted patents·2 pending applications·26 citations·filing 2005–2014
Top patents by PatentIndex Score
11 records- 0189US9184117B2Stacked dual-chip packaging structure and preparation method thereofHO YUEH-SE·Filed 2012·Granted Nov 10, 2015·11 cites·18 claims
- 0283US9214417B2Combined packaged power semiconductor deviceHO YUEH-SE·Filed 2014·Granted Dec 15, 2015·5 cites·6 claims
- 0378US8686546B2Combined packaged power semiconductor deviceHO YUEH-SE·Filed 2011·Granted Apr 1, 2014·5 cites·23 claims
- 0468US8217503B2Package structure for DC-DC converterHO YUEH-SE·Filed 2010·Granted Jul 10, 2012·2 cites·14 claims
- 0565US8865523B2Semiconductor package and fabrication method thereofHO YUEH-SE·Filed 2013·Granted Oct 21, 2014·1 cites·8 claims
- 0664US8569169B2Bottom source power MOSFET with substrateless and manufacturing method thereofHO YUEH-SE·Filed 2011·Granted Oct 29, 2013·2 cites·8 claims
- 0749US8890296B2Wafer level chip scale packageHO YUEH-SE·Filed 2013·Granted Nov 18, 2014·0 cites·11 claims
- 0849US8476752B2Package structure for DC-DC converterHO YUEH-SE·Filed 2012·Granted Jul 2, 2013·0 cites·8 claims
- 0942US9136379B2Bottom source substrateless power MOSFETHO YUEH-SE·Filed 2013·Granted Sep 15, 2015·0 cites·9 claims
- 1040US2007075406A1Wafer-level method for metallizing source, gate and drain contact areas of semiconductor dieHO YUEH-SE·Filed 2005·Application pending·0 cites
- 1140US2007057368A1Semiconductor package having plate interconnectionsHO YUEH-SE·Filed 2005·Application pending·0 cites
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