Assignee
IP FIRST LLC
US153 patents
Top patents by PatentIndex Score
US6832296B2Dec 14, 2004
Microprocessor with repeat prefetch instruction
IP FIRST LLC143 citations99
US6681311B2Jan 20, 2004
Translation lookaside buffer that caches memory type information
IP FIRST LLC71 citations98
US6647489B1Nov 11, 2003
Compare branch instruction pairing within a single integer pipeline
IP FIRST LLC76 citations98
US6571331B2May 27, 2003
Static branch prediction mechanism for conditional branch instructions
IP FIRST LLC112 citations98
US6338136B1Jan 8, 2002
Pairing of load-ALU-store with conditional branch
IP FIRST LLC89 citations98
US7546446B2Jun 9, 2009
Selective interrupt suppression
IP FIRST LLC65 citations97
US7065632B1Jun 20, 2006
Method and apparatus for speculatively forwarding storehit data in a hierarchical manner
IP FIRST LLC65 citations96
US6886093B2Apr 26, 2005
Speculative hybrid branch direction predictor
IP FIRST LLC56 citations96
US6609194B1Aug 19, 2003
Apparatus for performing branch target address calculation based on branch type
IP FIRST LLC69 citations96
US6550004B1Apr 15, 2003
Hybrid branch predictor with improved selector table update mechanism
IP FIRST LLC65 citations96
US6314514B1Nov 6, 2001
Method and apparatus for correcting an internal call/return stack in a microprocessor that speculatively executes call and return instructions
IP FIRST LLC76 citations96
US6189091B1Feb 13, 2001
Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection
IP FIRST LLC53 citations96
US6108773AAug 22, 2000
Apparatus and method for branch target address calculation during instruction decode
IP FIRST LLC71 citations96
US7844053B2Nov 30, 2010
Microprocessor apparatus and method for performing block cipher cryptographic functions
IP FIRST LLC29 citations93
US7543134B2Jun 2, 2009
Apparatus and method for extending a microprocessor instruction set
IP FIRST LLC16 citations93
US7373483B2May 13, 2008
Mechanism for extending the number of registers in a microprocessor
IP FIRST LLC24 citations93
US7321910B2Jan 22, 2008
Microprocessor apparatus and method for performing block cipher cryptographic functions
IP FIRST LLC36 citations93
US7315921B2Jan 1, 2008
Apparatus and method for selective memory attribute control
IP FIRST LLC19 citations93
US7181596B2Feb 20, 2007
Apparatus and method for extending a microprocessor instruction set
IP FIRST LLC39 citations93
US7174355B2Feb 6, 2007
Random number generator with selectable dual random bit string engines
IP FIRST LLC23 citations93
US7149764B2Dec 12, 2006
Random number generator bit string filter
IP FIRST LLC23 citations93
US6985999B2Jan 10, 2006
Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests
IP FIRST LLC21 citations93
US6949949B2Sep 27, 2005
Apparatus and method for adjusting the impedance of an output driver
IP FIRST LLC19 citations93
US6931517B1Aug 16, 2005
Pop-compare micro instruction for repeat string operations
IP FIRST LLC25 citations93
US6870407B2Mar 22, 2005
Thin gate oxide output drive
IP FIRST LLC20 citations93
US6871206B2Mar 22, 2005
Continuous multi-buffering random number generator
IP FIRST LLC38 citations93
US6810466B2Oct 26, 2004
Microprocessor and method for performing selective prefetch based on bus activity level
IP FIRST LLC42 citations93
US6629234B1Sep 30, 2003
Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction
IP FIRST LLC25 citations93
US6622211B2Sep 16, 2003
Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty
IP FIRST LLC32 citations93
US6581151B2Jun 17, 2003
Apparatus and method for speculatively forwarding storehit data based on physical page index compare
IP FIRST LLC20 citations93
US6553473B1Apr 22, 2003
Byte-wise tracking on write allocate
IP FIRST LLC30 citations93
US6370661B1Apr 9, 2002
Apparatus for testing memory in a microprocessor
IP FIRST LLC47 citations93
US6343359B1Jan 29, 2002
Result forwarding cache
IP FIRST LLC20 citations93
US6330657B1Dec 11, 2001
Pairing of micro instructions in the instruction queue
IP FIRST LLC43 citations93
US6247122B1Jun 12, 2001
Method and apparatus for performing branch prediction combining static and dynamic branch predictors
IP FIRST LLC51 citations93
US6233676B1May 15, 2001
Apparatus and method for fast forward branch
IP FIRST LLC43 citations93
US6161188ADec 12, 2000
Microprocessor having fuse control and selection of clock multiplier
IP FIRST LLC21 citations93
US6145075ANov 7, 2000
Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file
IP FIRST LLC26 citations93
US6009510ADec 28, 1999
Method and apparatus for improved aligned/misaligned data load from cache
IP FIRST LLC41 citations93
US7532722B2May 12, 2009
Apparatus and method for performing transparent block cipher cryptographic functions
IP FIRST LLC40 citations92
US7237098B2Jun 26, 2007
Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
IP FIRST LLC22 citations92
US7203824B2Apr 10, 2007
Apparatus and method for handling BTAC branches that wrap across instruction cache lines
IP FIRST LLC24 citations92
US7165169B2Jan 16, 2007
Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
IP FIRST LLC28 citations92
US7117347B2Oct 3, 2006
Processor including fallback branch prediction mechanism for far jump and far call instructions
IP FIRST LLC42 citations92
US6895498B2May 17, 2005
Apparatus and method for target address replacement in speculative branch target address cache
IP FIRST LLC45 citations92
US6823444B1Nov 23, 2004
Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
IP FIRST LLC47 citations92
US6609191B1Aug 19, 2003
Method and apparatus for speculative microinstruction pairing
IP FIRST LLC19 citations92
US6526502B1Feb 25, 2003
Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome
IP FIRST LLC38 citations92
US6405306B2Jun 11, 2002
Instruction set for bi-directional conversion and transfer of integer and floating point data
IP FIRST LLC22 citations92
US6349383B1Feb 19, 2002
System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution
IP FIRST LLC42 citations92
Showing the top 50 of 153 patents by PatentIndex Score.