Assignee
ISHIZU TOMOYUKI
JP·2 granted patents·6 citations·filing 2011–2012
Top patents by PatentIndex Score
2 records- 0166US8575703B2Semiconductor device layout reducing imbalance characteristics of paired transistorsISHIZU TOMOYUKI·Filed 2011·Granted Nov 5, 2013·3 cites·14 claims
- 0266US8555224B2Circuit simulation method and semiconductor integrated circuitISHIZU TOMOYUKI·Filed 2012·Granted Oct 8, 2013·3 cites·20 claims
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