Assignee
IYER ARUN
IN·3 granted patents·11 citations·filing 2009–2011
Top patents by PatentIndex Score
3 records- 0167US8584065B2Method and apparatus for designing an integrated circuitIYER ARUN·Filed 2011·Granted Nov 12, 2013·5 cites·20 claims
- 0265US8120406B2Sequential circuit with dynamic pulse width controlIYER ARUN·Filed 2009·Granted Feb 21, 2012·6 cites·9 claims
- 0337US8504866B2Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameterIYER ARUN·Filed 2010·Granted Aug 6, 2013·0 cites·14 claims
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