Assignee
JASPER DESIGN AUTOMATION INC
US·19 granted patents·317 citations·filing 2000–2014
Technology mixG06F19
Top patents by PatentIndex Score
19 records- 0190US7895552B1Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstractionJASPER DESIGN AUTOMATION INC·Filed 2005·Granted Feb 22, 2011·30 cites·33 claims
- 0289US9449196B1Security data path verificationJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Sep 20, 2016·15 cites·26 claims
- 0384US8984461B1Visualization constraints for circuit designsJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Mar 17, 2015·7 cites·24 claims
- 0483US8990745B1Manipulation of traces for debugging behaviors of a circuit designJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Mar 24, 2015·6 cites·20 claims
- 0583US7506288B1Interactive analysis and debugging of a circuit design during functional verification of the circuit designJASPER DESIGN AUTOMATION INC·Filed 2005·Granted Mar 17, 2009·13 cites·21 claims
- 0682US9081927B2Manipulation of traces for debugging a circuit designJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Jul 14, 2015·5 cites·20 claims
- 0782US7421668B1Meaningful visualization of properties independent of a circuit designJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Sep 2, 2008·37 cites·55 claims
- 0882US7065726B1System and method for guiding and optimizing formal verification for a circuit designJASPER DESIGN AUTOMATION INC·Filed 2003·Granted Jun 20, 2006·36 cites·26 claims
- 0981US9158874B1Formal verification coverage metrics of covered events for circuit design propertiesJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Oct 13, 2015·6 cites·20 claims
- 1081US9104824B1Power aware retention flop list analysis and modificationJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Aug 11, 2015·9 cites·22 claims
- 1180US8954904B1Veryifing low power functionality through RTL transformationJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Feb 10, 2015·8 cites·20 claims
- 1280US7647572B1Managing formal verification complexity of designs with multiple related countersJASPER DESIGN AUTOMATION INC·Filed 2007·Granted Jan 12, 2010·9 cites·24 claims
- 1379US8826201B1Formal verification coverage metrics for circuit design propertiesJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Sep 2, 2014·5 cites·18 claims
- 1479US7020856B2Method for verifying properties of a circuit modelJASPER DESIGN AUTOMATION INC·Filed 2003·Granted Mar 28, 2006·27 cites·25 claims
- 1579US6611947B1Method for determining the functional equivalence between two circuit models in a distributed computing environmentJASPER DESIGN AUTOMATION INC·Filed 2000·Granted Aug 26, 2003·37 cites·16 claims
- 1677US7418678B1Managing formal verification complexity of designs with countersJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Aug 26, 2008·21 cites·29 claims
- 1777US7137078B2Trace based method for design navigationJASPER DESIGN AUTOMATION INC·Filed 2003·Granted Nov 14, 2006·30 cites·14 claims
- 1868US7237208B1Managing formal verification complexity of designs with datapathsJASPER DESIGN AUTOMATION INC·Filed 2004·Granted Jun 26, 2007·14 cites·15 claims
- 1967US9460252B1Functional property rankingJASPER DESIGN AUTOMATION INC·Filed 2014·Granted Oct 4, 2016·2 cites·22 claims
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