Assignee
KELLER IGOR
US5 patents
Top patents by PatentIndex Score
US8595669B1Nov 26, 2013
Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
KELLER IGOR39 citations93
US8543954B1Sep 24, 2013
Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
KELLER IGOR28 citations92
US8302046B1Oct 30, 2012
Compact modeling of circuit stages for static timing analysis of integrated circuit designs
KELLER IGOR20 citations92
US8601420B1Dec 3, 2013
Equivalent waveform model for static timing analysis of integrated circuit designs
KELLER IGOR27 citations91
US8615725B1Dec 24, 2013
Methods for compact modeling of circuit stages for static timing analysis of integrated circuit designs
KELLER IGOR10 citations83