Assignee
LIAO CHIH-CHIN
TW·5 granted patents·4 pending applications·26 citations·filing 2006–2012
Top patents by PatentIndex Score
9 records- 0192US8415808B2Semiconductor device with die stack arrangement including staggered die and efficient wire bondingLIAO CHIH-CHIN·Filed 2010·Granted Apr 9, 2013·24 cites·8 claims
- 0266US8502375B2Corrugated die edge for stacked die semiconductor packageLIAO CHIH-CHIN·Filed 2010·Granted Aug 6, 2013·2 cites·34 claims
- 0357US9006912B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2012·Granted Apr 14, 2015·0 cites·14 claims
- 0453US8217522B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2010·Granted Jul 10, 2012·0 cites·13 claims
- 0544US8637972B2Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panelLIAO CHIH-CHIN·Filed 2007·Granted Jan 28, 2014·0 cites·30 claims
- 0641US2007267759A1Semiconductor device with a distributed plating patternLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 0741US2007235848A1Substrate having conductive traces isolated by laser to allow electrical inspectionLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 0841US2007269929A1Method of reducing stress on a semiconductor die with a distributed plating patternLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 0935US2013015589A1Chip-on-package structure for multiple die stacksLIAO CHIH-CHIN·Filed 2011·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →