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MANOVIT CHAIYASIT
US4 patents
Top patents by PatentIndex Score
US8099703B1Jan 17, 2012
Method and system for verifying power-optimized electronic designs using equivalency checking
MANOVIT CHAIYASIT14 citations82
US8219946B1Jul 10, 2012
Method for clock gating circuits
MANOVIT CHAIYASIT11 citations80
US8423935B1Apr 16, 2013
Method and apparatus for verifying output-based clock gating
MANOVIT CHAIYASIT4 citations58
US8898401B2Nov 25, 2014
Methods and apparatuses for improving speculation success in processors
MANOVIT CHAIYASIT1 citations45