Assignee
MARATHE VIRENDRA J
US·7 granted patents·29 citations·filing 2010–2011
Technology mixG06F7
Top patents by PatentIndex Score
7 records- 0191US8458721B2System and method for implementing hierarchical queue-based locks using flat combiningMARATHE VIRENDRA J·Filed 2011·Granted Jun 4, 2013·18 cites·20 claims
- 0272US8732682B2Systems and methods for detecting and tolerating atomicity violations between concurrent code blocksMARATHE VIRENDRA J·Filed 2011·Granted May 20, 2014·3 cites·20 claims
- 0371US8417897B2System and method for providing locale-based optimizations in a transactional memoryMARATHE VIRENDRA J·Filed 2010·Granted Apr 9, 2013·3 cites·20 claims
- 0466US8473952B2System and method for communication between concurrent transactions using transaction communicator objectsMARATHE VIRENDRA J·Filed 2010·Granted Jun 25, 2013·2 cites·20 claims
- 0561US8677331B2Lock-clustering compilation for software transactional memoryMARATHE VIRENDRA J·Filed 2011·Granted Mar 18, 2014·1 cites·20 claims
- 0659US9424015B2System and method for optimizing software transactional memory operations using static caching of memory objectsMARATHE VIRENDRA J·Filed 2011·Granted Aug 23, 2016·2 cites·20 claims
- 0743US9430275B2Synchronization between concurrent notifier and waiter transactions using transaction condition variablesMARATHE VIRENDRA J·Filed 2011·Granted Aug 30, 2016·0 cites·20 claims
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