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MIPS TECH INC

US238 patents

Top patents by PatentIndex Score

US7321965B2Jan 22, 2008

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

MIPS TECH INC100 citations99

US7177985B1Feb 13, 2007

Microprocessor with improved data stream prefetching

MIPS TECH INC153 citations99

US5933650AAug 3, 1999

Alignment and ordering of vector elements for single instruction multiple data processing

MIPS TECH INC352 citations99

US5864703AJan 26, 1999

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor

MIPS TECH INC63 citations98

US7376954B2May 20, 2008

Mechanisms for assuring quality of service for programs executing on a multithreaded processor

MIPS TECH INC77 citations98

US7257814B1Aug 14, 2007

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

MIPS TECH INC99 citations98

US7197625B1Mar 27, 2007

Alignment and ordering of vector elements for single instruction multiple data processing

MIPS TECH INC61 citations98

US7185183B1Feb 27, 2007

Atomic update of CPO state

MIPS TECH INC96 citations98

US7185234B1Feb 27, 2007

Trace control from hardware and software

MIPS TECH INC70 citations98

US7181600B1Feb 20, 2007

Read-only access to CPO registers

MIPS TECH INC73 citations98

US7178133B1Feb 13, 2007

Trace control based on a characteristic of a processor's operating state

MIPS TECH INC62 citations98

US7020879B1Mar 28, 2006

Interrupt and exception handling for multi-streaming digital processors

MIPS TECH INC143 citations98

US6697832B1Feb 24, 2004

Floating-point processor with improved intermediate result handling

MIPS TECH INC77 citations98

US6681283B1Jan 20, 2004

Coherent data apparatus for an on-chip split transaction system bus

MIPS TECH INC77 citations98

US6490642B1Dec 3, 2002

Locked read/write on separate address/data bus using write barrier

MIPS TECH INC80 citations98

US6393500B1May 21, 2002

Burst-configurable data bus

MIPS TECH INC104 citations98

US7242414B1Jul 10, 2007

Processor having a compare extension of an instruction set architecture

MIPS TECH INC71 citations97

US7181484B2Feb 20, 2007

Extended-precision accumulation of multiplier output

MIPS TECH INC101 citations97

US7149878B1Dec 12, 2006

Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values

MIPS TECH INC85 citations97

US7055070B1May 30, 2006

Trace control block implementation and method

MIPS TECH INC122 citations97

US7032226B1Apr 18, 2006

Methods and apparatus for managing a buffer of events in the background

MIPS TECH INC69 citations97

US6789100B2Sep 7, 2004

Interstream control and communications for multi-streaming digital processors

MIPS TECH INC80 citations97

US6754804B1Jun 22, 2004

Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions

MIPS TECH INC130 citations97

US6594728B1Jul 15, 2003

Cache memory with dual-way arrays and multiplexed parallel output

MIPS TECH INC133 citations97

US6493776B1Dec 10, 2002

Scalable on-chip system bus

MIPS TECH INC95 citations97

US6266758B1Jul 24, 2001

Alignment and ordering of vector elements for single instruction multiple data processing

MIPS TECH INC193 citations97

US7747989B1Jun 29, 2010

Virtual machine coprocessor facilitating dynamic compilation

MIPS TECH INC44 citations96

US7676660B2Mar 9, 2010

System, method, and computer program product for conditionally suspending issuing instructions of a thread

MIPS TECH INC41 citations96

US7610473B2Oct 27, 2009

Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

MIPS TECH INC48 citations96

US7512740B2Mar 31, 2009

Microprocessor with improved data stream prefetching

MIPS TECH INC31 citations96

US7139898B1Nov 21, 2006

Fetch and dispatch disassociation apparatus for multistreaming processors

MIPS TECH INC44 citations96

US7069544B1Jun 27, 2006

Dynamic selection of a compression algorithm for trace data

MIPS TECH INC46 citations96

US7043668B1May 9, 2006

Optimized external trace formats

MIPS TECH INC75 citations96

US7035997B1Apr 25, 2006

Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors

MIPS TECH INC61 citations96

US6976178B1Dec 13, 2005

Method and apparatus for disassociating power consumed within a processing system with instructions it is executing

MIPS TECH INC64 citations96

US6651160B1Nov 18, 2003

Register set extension for compressed instruction set

MIPS TECH INC80 citations96

US6625737B1Sep 23, 2003

System for prediction and control of power consumption in digital system

MIPS TECH INC65 citations96

US6430655B1Aug 6, 2002

Scratchpad RAM memory accessible in parallel to a primary cache

MIPS TECH INC70 citations96

US6092187AJul 18, 2000

Instruction prediction based on filtering

MIPS TECH INC51 citations96

US6742165B2May 25, 2004

System, method and computer program product for web-based integrated circuit design

MIPS TECH INC108 citations95

US6691221B2Feb 10, 2004

Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution

MIPS TECH INC52 citations95

US6266755B1Jul 24, 2001

Translation lookaside buffer with virtual address conflict prevention

MIPS TECH INC62 citations95

US6247124B1Jun 12, 2001

Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions

MIPS TECH INC47 citations95

US7134116B1Nov 7, 2006

External trace synchronization via periodic sampling

MIPS TECH INC50 citations94

US7035998B1Apr 25, 2006

Clustering stream and/or instruction queues for multi-streaming processors

MIPS TECH INC68 citations94

US6240488B1May 29, 2001

Prefetching hints

MIPS TECH INC54 citations94

US6216200B1Apr 10, 2001

Address queue

MIPS TECH INC165 citations94

Showing the top 50 of 238 patents by PatentIndex Score.

MIPS TECH INC

Top patents by PatentIndex Score

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Microprocessor with improved data stream prefetching

Alignment and ordering of vector elements for single instruction multiple data processing

Method for providing extended precision in SIMD vector arithmetic operations

Mechanisms for dynamic configuration of virtual processor resources

Instruction encoding for system register bit set and clear

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor

Mechanisms for assuring quality of service for programs executing on a multithreaded processor

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Alignment and ordering of vector elements for single instruction multiple data processing

Atomic update of CPO state

Trace control from hardware and software

Read-only access to CPO registers

Trace control based on a characteristic of a processor&#39;s operating state

Interrupt and exception handling for multi-streaming digital processors

Floating-point processor with improved intermediate result handling

Coherent data apparatus for an on-chip split transaction system bus

Locked read/write on separate address/data bus using write barrier

Burst-configurable data bus

Processor having a compare extension of an instruction set architecture

Extended-precision accumulation of multiplier output

Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values

Trace control block implementation and method

Methods and apparatus for managing a buffer of events in the background

Interstream control and communications for multi-streaming digital processors

Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions

Cache memory with dual-way arrays and multiplexed parallel output

Scalable on-chip system bus

Alignment and ordering of vector elements for single instruction multiple data processing

Virtual machine coprocessor facilitating dynamic compilation

System, method, and computer program product for conditionally suspending issuing instructions of a thread

Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Microprocessor with improved data stream prefetching

Fetch and dispatch disassociation apparatus for multistreaming processors

Dynamic selection of a compression algorithm for trace data

Optimized external trace formats

Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors

Method and apparatus for disassociating power consumed within a processing system with instructions it is executing

Register set extension for compressed instruction set

System for prediction and control of power consumption in digital system

Scratchpad RAM memory accessible in parallel to a primary cache

Instruction prediction based on filtering

System, method and computer program product for web-based integrated circuit design

Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution

Translation lookaside buffer with virtual address conflict prevention

Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions

External trace synchronization via periodic sampling

Clustering stream and/or instruction queues for multi-streaming processors

Prefetching hints

Address queue

Trace control based on a characteristic of a processor's operating state