Assignee
MONTEREY DESIGN SYSTEMS
US·3 granted patents·162 citations·filing 1998–1998
Technology mixG06F3
Top patents by PatentIndex Score
3 records- 0187US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0249US6192508B1Method for logic optimization for improving timing and congestion during placement in integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Feb 20, 2001·23 cites·18 claims
- 0339US6449756B1Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Sep 10, 2002·13 cites·23 claims
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