Assignee
MOROZ VICTOR
US20 patents
Top patents by PatentIndex Score
US8407634B1Mar 26, 2013
Analysis of stress impact on transistor performance
MOROZ VICTOR10 citations93
US8723268B2May 13, 2014
N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch
MOROZ VICTOR26 citations92
US8901615B2Dec 2, 2014
N-channel and P-channel end-to-end finfet cell architecture
MOROZ VICTOR16 citations84
US8069430B2Nov 29, 2011
Stress-managed revision of integrated circuit layouts
MOROZ VICTOR8 citations84
US9064808B2Jun 23, 2015
Integrated circuit devices having features with reduced edge curvature and methods for manufacturing the same
MOROZ VICTOR6 citations83
US8609550B2Dec 17, 2013
Methods for manufacturing integrated circuit devices having features with reduced edge curvature
MOROZ VICTOR11 citations83
US8661398B1Feb 25, 2014
Analysis of stress impact on transistor performance
MOROZ VICTOR2 citations74
US8615728B2Dec 24, 2013
Analysis of stress impact on transistor performance
MOROZ VICTOR4 citations74
US8686512B2Apr 1, 2014
Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance
MOROZ VICTOR4 citations73
US8701054B2Apr 15, 2014
Boosting transistor performance with non-rectangular channels
MOROZ VICTOR5 citations71
US8713510B2Apr 29, 2014
Analysis of stress impact on transistor performance
MOROZ VICTOR1 citations63
US9287253B2Mar 15, 2016
Method and apparatus for floating or applying voltage to a well of an integrated circuit
MOROZ VICTOR2 citations62
US8219961B2Jul 10, 2012
Method for compensation of process-induced performance variation in a MOSFET integrated circuit
MOROZ VICTOR3 citations61
US9917018B2Mar 13, 2018
Method and apparatus with channel stop doped devices
MOROZ VICTOR1 citations52
US9190346B2Nov 17, 2015
Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
MOROZ VICTOR0 citations52
US8881073B1Nov 4, 2014
Analysis of stress impact on transistor performance
MOROZ VICTOR0 citations52
US8762924B2Jun 24, 2014
Analysis of stress impact on transistor performance
MOROZ VICTOR0 citations52
US8560995B2Oct 15, 2013
Analysis of stress impact on transistor performance
MOROZ VICTOR0 citations52
US8413096B2Apr 2, 2013
Analysis of stress impact on transistor performance
MOROZ VICTOR0 citations52
US9472423B2Oct 18, 2016
Method for suppressing lattice defects in a semiconductor substrate
MOROZ VICTOR0 citations42