Assignee

Netspeed Systems

US52 patents

Top patents by PatentIndex Score

US8667439B1Mar 4, 2014

Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Netspeed Systems92 citations98

US8601423B1Dec 3, 2013

Asymmetric mesh NoC topologies

Netspeed Systems118 citations98

US9444702B1Sep 13, 2016

System and method for visualization of NoC performance based on simulation output

Netspeed Systems55 citations97

US8819611B2Aug 26, 2014

Asymmetric mesh NoC topologies

Netspeed Systems60 citations97

US9568970B1Feb 14, 2017

Hardware and software enabled implementation of power profile management instructions in system on chip

Netspeed Systems59 citations95

US9742630B2Aug 22, 2017

Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements

Netspeed Systems37 citations94

US9473359B2Oct 18, 2016

Transactional traffic specification for network-on-chip design

Netspeed Systems24 citations94

US9473388B2Oct 18, 2016

Supporting multicast in NOC interconnect

Netspeed Systems30 citations94

US9473415B2Oct 18, 2016

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Netspeed Systems26 citations94

US9319232B2Apr 19, 2016

Integrated NoC for performing data communication and NoC functions

Netspeed Systems25 citations94

US9294354B2Mar 22, 2016

Using multiple traffic profiles to design a network on chip

Netspeed Systems26 citations94

US9223711B2Dec 29, 2015

Combining associativity and cuckoo hashing

Netspeed Systems47 citations94

US9660942B2May 23, 2017

Automatic buffer sizing for optimal network-on-chip design

Netspeed Systems20 citations93

US9571341B1Feb 14, 2017

Clock gating for system-on-chip elements

Netspeed Systems43 citations93

US9535848B2Jan 3, 2017

Using cuckoo movement for improved cache coherency

Netspeed Systems26 citations93

US9477280B1Oct 25, 2016

Specification for automatic power management of network-on-chip and system-on-chip

Netspeed Systems32 citations93

US9471726B2Oct 18, 2016

System level simulation in network on chip architecture

Netspeed Systems25 citations93

US9244845B2Jan 26, 2016

System and method for improving snoop performance

Netspeed Systems28 citations93

US8885510B2Nov 11, 2014

Heterogeneous channel capacities in an interconnect

Netspeed Systems30 citations92

US8819616B2Aug 26, 2014

Asymmetric mesh NoC topologies

Netspeed Systems23 citations92

US10027433B2Jul 17, 2018

Multiple clock domains in NoC

Netspeed Systems7 citations84

US9185023B2Nov 10, 2015

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Netspeed Systems8 citations84

US8934377B2Jan 13, 2015

Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis

Netspeed Systems9 citations84

US10496770B2Dec 3, 2019

System level simulation in Network on Chip architecture

Netspeed Systems6 citations83

US10042404B2Aug 7, 2018

Automatic generation of power management sequence in a SoC or NoC

Netspeed Systems5 citations83

US9054977B2Jun 9, 2015

Automatic NoC topology generation

Netspeed Systems10 citations83

US10528682B2Jan 7, 2020

Automatic performance characterization of a network-on-chip (NOC) interconnect

Netspeed Systems2 citations73

US10050843B2Aug 14, 2018

Generation of network-on-chip layout based on user specified topological constraints

Netspeed Systems5 citations73

US9864728B2Jan 9, 2018

Automatic generation of physically aware aggregation/distribution networks

Netspeed Systems3 citations73

US9158882B2Oct 13, 2015

Automatic pipelining of NoC channels to meet timing and/or performance

Netspeed Systems4 citations73

US10324509B2Jun 18, 2019

Automatic generation of power management sequence in a SoC or NoC

Netspeed Systems2 citations72

US9830265B2Nov 28, 2017

Reuse of directory entries for holding state information through use of multiple formats

Netspeed Systems3 citations72

US10218580B2Feb 26, 2019

Generating physically aware network-on-chip design from a physical system-on-chip specification

Netspeed Systems4 citations71

US9785732B2Oct 10, 2017

Verification low power collateral generation

Netspeed Systems5 citations68

US10554496B2Feb 4, 2020

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Netspeed Systems1 citations63

US10110499B2Oct 23, 2018

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Netspeed Systems1 citations63

US9769077B2Sep 19, 2017

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Netspeed Systems1 citations63

US10355996B2Jul 16, 2019

Heterogeneous channel capacities in an interconnect

Netspeed Systems1 citations62

US10218581B2Feb 26, 2019

Generation of network-on-chip layout based on user specified topological constraints

Netspeed Systems0 citations52

US9825809B2Nov 21, 2017

Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip

Netspeed Systems1 citations52

US9781043B2Oct 3, 2017

Identification of internal dependencies within system components for evaluating potential protocol level deadlocks

Netspeed Systems1 citations52

US9774498B2Sep 26, 2017

Hierarchical asymmetric mesh with virtual routers

Netspeed Systems1 citations52

US9762474B2Sep 12, 2017

Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)

Netspeed Systems0 citations52

US9563735B1Feb 7, 2017

Automatic pipelining of NoC channels to meet timing and/or performance

Netspeed Systems0 citations52

Showing the top 50 of 52 patents by PatentIndex Score.

Netspeed Systems

Top patents by PatentIndex Score

Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Asymmetric mesh NoC topologies

System and method for visualization of NoC performance based on simulation output

Asymmetric mesh NoC topologies

Hardware and software enabled implementation of power profile management instructions in system on chip

Configurable router for a network on chip (NoC)

Streaming bridge design with host interfaces and network on chip (NoC) layers

Supporting multicast in NoC interconnect

Automatic pipelining of NoC channels to meet timing and/or performance

Integrated NoC for performing data communication and NoC functions

Congestion control and QoS in NoC by regulating the injection traffic

Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements

Transactional traffic specification for network-on-chip design

Supporting multicast in NOC interconnect

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Integrated NoC for performing data communication and NoC functions

Using multiple traffic profiles to design a network on chip

Combining associativity and cuckoo hashing

Automatic buffer sizing for optimal network-on-chip design

Clock gating for system-on-chip elements

Using cuckoo movement for improved cache coherency

Specification for automatic power management of network-on-chip and system-on-chip

System level simulation in network on chip architecture

System and method for improving snoop performance

Heterogeneous channel capacities in an interconnect

Asymmetric mesh NoC topologies

Multiple clock domains in NoC

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis

System level simulation in Network on Chip architecture

Automatic generation of power management sequence in a SoC or NoC

Automatic NoC topology generation

Automatic performance characterization of a network-on-chip (NOC) interconnect

Generation of network-on-chip layout based on user specified topological constraints

Automatic generation of physically aware aggregation/distribution networks

Automatic pipelining of NoC channels to meet timing and/or performance

Automatic generation of power management sequence in a SoC or NoC

Reuse of directory entries for holding state information through use of multiple formats

Generating physically aware network-on-chip design from a physical system-on-chip specification

Verification low power collateral generation

Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance

QoS in a system with end-to-end flow control and QoS aware buffer allocation

QoS in a system with end-to-end flow control and QoS aware buffer allocation

Heterogeneous channel capacities in an interconnect

Generation of network-on-chip layout based on user specified topological constraints

Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip

Identification of internal dependencies within system components for evaluating potential protocol level deadlocks

Hierarchical asymmetric mesh with virtual routers

Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)

Automatic pipelining of NoC channels to meet timing and/or performance