Assignee
PURUSHOTHAMAN SAMPATH
US·7 granted patents·1 pending application·58 citations·filing 2008–2013
Top patents by PatentIndex Score
8 records- 0195US8093099B2Lock and key through-via method for wafer level 3D integration and structures producedPURUSHOTHAMAN SAMPATH·Filed 2010·Granted Jan 10, 2012·27 cites·10 claims
- 0291US8314005B2Homogeneous porous low dielectric constant materialsPURUSHOTHAMAN SAMPATH·Filed 2011·Granted Nov 20, 2012·12 cites·13 claims
- 0389US8563396B23D integration method using SOI substrates and structures produced therebyPURUSHOTHAMAN SAMPATH·Filed 2011·Granted Oct 22, 2013·8 cites·8 claims
- 0479US9064717B2Lock and key through-via method for wafer level 3D integration and structures produced therebyPURUSHOTHAMAN SAMPATH·Filed 2009·Granted Jun 23, 2015·8 cites·16 claims
- 0571US8778736B2Capping coating for 3D integration applicationsPURUSHOTHAMAN SAMPATH·Filed 2008·Granted Jul 15, 2014·2 cites·17 claims
- 0665US8623741B2Homogeneous porous low dielectric constant materialsPURUSHOTHAMAN SAMPATH·Filed 2012·Granted Jan 7, 2014·1 cites·18 claims
- 0756US8912050B2Capping coating for 3D integration applicationsPURUSHOTHAMAN SAMPATH·Filed 2012·Granted Dec 16, 2014·0 cites·9 claims
- 0843US2017271207A9Novel 3D Integration Method Using SOI Substrates And Structures Produced TherebyPURUSHOTHAMAN SAMPATH·Filed 2013·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →