Assignee
RAO VISHWAS M
US·5 granted patents·29 citations·filing 2009–2012
Top patents by PatentIndex Score
5 records- 0184US8341573B2Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flowRAO VISHWAS M·Filed 2010·Granted Dec 25, 2012·8 cites·7 claims
- 0282US8239805B2Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the methodRAO VISHWAS M·Filed 2009·Granted Aug 7, 2012·9 cites·10 claims
- 0381US8539419B2Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the methodRAO VISHWAS M·Filed 2012·Granted Sep 17, 2013·5 cites·9 claims
- 0467US8122422B2Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus thereforRAO VISHWAS M·Filed 2009·Granted Feb 21, 2012·6 cites·20 claims
- 0561US8689161B2Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design toolsRAO VISHWAS M·Filed 2010·Granted Apr 1, 2014·1 cites·20 claims
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