Assignee
RICHTER RALF
DE18 patents
Top patents by PatentIndex Score
US8951907B2Feb 10, 2015
Semiconductor devices having through-contacts and related fabrication methods
RICHTER RALF7 citations84
US8258062B2Sep 4, 2012
Cap layer removal in a high-K metal gate stack by using an etch process
RICHTER RALF8 citations83
US8426312B2Apr 23, 2013
Method of reducing contamination by providing an etch stop layer at the substrate edge
RICHTER RALF5 citations72
US9136319B2Sep 15, 2015
Method of making capacitor with a sealing liner and semiconductor device comprising same
RICHTER RALF2 citations63
US8216928B1Jul 10, 2012
Methods for fabricating semiconductor devices having local contacts
RICHTER RALF4 citations62
US8129276B2Mar 6, 2012
Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors
RICHTER RALF3 citations62
US8906801B2Dec 9, 2014
Processes for forming integrated circuits and integrated circuits formed thereby
RICHTER RALF2 citations60
US8198190B2Jun 12, 2012
Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
RICHTER RALF3 citations60
US8697584B2Apr 15, 2014
Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device
RICHTER RALF0 citations52
US8324108B2Dec 4, 2012
Increasing robustness of a dual stress liner approach in a semiconductor device by applying a wet chemistry
RICHTER RALF0 citations52
US8216927B2Jul 10, 2012
Method of reducing contamination by providing a removable polymer protection film during microstructure processing
RICHTER RALF1 citations52
US8435841B2May 7, 2013
Enhancement of ultraviolet curing of tensile stress liner using reflective materials
RICHTER RALF1 citations51
US8741770B2Jun 3, 2014
Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
RICHTER RALF0 citations50
US9034744B2May 19, 2015
Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material
RICHTER RALF0 citations42
US8722511B2May 13, 2014
Reduced topography in isolation regions of a semiconductor device by applying a deposition/etch sequence prior to forming the interlayer dielectric
RICHTER RALF0 citations42
US8658509B2Feb 25, 2014
Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates
RICHTER RALF0 citations42
US8450172B2May 28, 2013
Non-insulating stressed material layers in a contact level of semiconductor devices
RICHTER RALF0 citations41
US8338314B2Dec 25, 2012
Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
RICHTER RALF0 citations41