Assignee
ROZAS GUILLERMO
11 granted patents·3 pending applications·251 citations·filing 2003–2012
Top patents by PatentIndex Score
14 records- 0198US8239656B2System and method for identifying TLB entries associated with a physical address of a specified rangeROZAS GUILLERMO·Filed 2011·Granted Aug 7, 2012·56 cites·20 claims
- 0297US7913058B2System and method for identifying TLB entries associated with a physical address of a specified rangeROZAS GUILLERMO·Filed 2008·Granted Mar 22, 2011·58 cites·26 claims
- 0396US8522253B1Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged cachesROZAS GUILLERMO·Filed 2006·Granted Aug 27, 2013·83 cites·13 claims
- 0492US7873793B1Supporting speculative modification in a data cacheROZAS GUILLERMO·Filed 2007·Granted Jan 18, 2011·24 cites·37 claims
- 0588US7606979B1Method and system for conservatively managing store capacity available to a processor issuing storesROZAS GUILLERMO·Filed 2006·Granted Oct 20, 2009·17 cites·42 claims
- 0676US7747896B1Dual ported replicated data cacheROZAS GUILLERMO·Filed 2006·Granted Jun 29, 2010·6 cites·25 claims
- 0768US7971002B1Maintaining instruction coherency in a translation-based computer system architectureROZAS GUILLERMO·Filed 2005·Granted Jun 28, 2011·4 cites·29 claims
- 0859US7904789B1Techniques for detecting and correcting errors in a memory deviceROZAS GUILLERMO·Filed 2006·Granted Mar 8, 2011·3 cites·28 claims
- 0954US2012254584A1System and method for identifying tlb entries associated with a physical address of a specified rangeROZAS GUILLERMO·Filed 2012·Application pending·0 cites
- 1050US2015149733A1Supporting speculative modification in a data cacheROZAS GUILLERMO·Filed 2011·Application pending·0 cites
- 1149US8656214B2Dual ported replicated data cacheROZAS GUILLERMO·Filed 2010·Granted Feb 18, 2014·0 cites·20 claims
- 1244US7725656B1Braided set associative caching techniquesROZAS GUILLERMO·Filed 2006·Granted May 25, 2010·0 cites·27 claims
- 1344US7606997B1Method and system for using one or more address bits and an instruction to increase an instruction setROZAS GUILLERMO·Filed 2003·Granted Oct 20, 2009·0 cites·14 claims
- 1440US2011131471A1Techniques for detecting and correcting errors in a memory deviceROZAS GUILLERMO·Filed 2011·Application pending·0 cites
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