Assignee
SEQUENCE DESIGN INC
US·26 granted patents·1,328 citations·filing 1999–2006
Top patents by PatentIndex Score
26 records- 0196US6643831B2Method and system for extraction of parasitic interconnect impedance including inductanceSEQUENCE DESIGN INC·Filed 2002·Granted Nov 4, 2003·275 cites·28 claims
- 0294US6698006B1Method for balanced-delay clock tree insertionSEQUENCE DESIGN INC·Filed 2001·Granted Feb 24, 2004·99 cites·41 claims
- 0393US6591407B1Method and apparatus for interconnect-driven optimization of integrated circuit designSEQUENCE DESIGN INC·Filed 2000·Granted Jul 8, 2003·146 cites·60 claims
- 0491US7509613B2Design method and architecture for power gate switch placement and interconnection using tapless librariesSEQUENCE DESIGN INC·Filed 2006·Granted Mar 24, 2009·29 cites·3 claims
- 0591US7323909B2Automatic extension of clock gating technique to fine-grained power gatingSEQUENCE DESIGN INC·Filed 2005·Granted Jan 29, 2008·30 cites·20 claims
- 0690US6754877B1Method for optimal driver selectionSEQUENCE DESIGN INC·Filed 2001·Granted Jun 22, 2004·53 cites·10 claims
- 0789US6701505B1Circuit optimization for minimum path timing violationsSEQUENCE DESIGN INC·Filed 2001·Granted Mar 2, 2004·54 cites·23 claims
- 0886US6701507B1Method for determining a zero-skew buffer insertion pointSEQUENCE DESIGN INC·Filed 2001·Granted Mar 2, 2004·44 cites·8 claims
- 0984US6807660B1Vectorless instantaneous current estimationSEQUENCE DESIGN INC·Filed 2002·Granted Oct 19, 2004·36 cites·11 claims
- 1083US6598209B1RTL power analysis using gate-level cell power modelsSEQUENCE DESIGN INC·Filed 2001·Granted Jul 22, 2003·55 cites·44 claims
- 1182US6291254B1Methods for determining on-chip interconnect process parametersSEQUENCE DESIGN INC·Filed 1999·Granted Sep 18, 2001·49 cites·19 claims
- 1281US6701506B1Method for match delay buffer insertionSEQUENCE DESIGN INC·Filed 2001·Granted Mar 2, 2004·32 cites·5 claims
- 1380US7222311B2Method and apparatus for interconnect-driven optimization of integrated circuit designSEQUENCE DESIGN INC·Filed 2003·Granted May 22, 2007·33 cites·16 claims
- 1480US6381730B1Method and system for extraction of parasitic interconnect impedance including inductanceSEQUENCE DESIGN INC·Filed 1999·Granted Apr 30, 2002·88 cites·32 claims
- 1579US7590962B2Design method and architecture for power gate switch placementSEQUENCE DESIGN INC·Filed 2004·Granted Sep 15, 2009·24 cites·34 claims
- 1679US7003741B2Method for determining load capacitanceSEQUENCE DESIGN INC·Filed 2004·Granted Feb 21, 2006·22 cites·7 claims
- 1777US6574787B1Method and apparatus for logic synthesis (word oriented netlist)SEQUENCE DESIGN INC·Filed 1999·Granted Jun 3, 2003·75 cites·16 claims
- 1877US6403389B1Method for determining on-chip sheet resistivitySEQUENCE DESIGN INC·Filed 1999·Granted Jun 11, 2002·42 cites·10 claims
- 1976US6312963B1Methods for determining on-chip interconnect process parametersSEQUENCE DESIGN INC·Filed 1999·Granted Nov 6, 2001·36 cites·4 claims
- 2074US6901565B2RTL power analysis using gate-level cell power modelsSEQUENCE DESIGN INC·Filed 2003·Granted May 31, 2005·24 cites·50 claims
- 2173US7117457B2Current scheduling system and method for optimizing multi-threshold CMOS designsSEQUENCE DESIGN INC·Filed 2003·Granted Oct 3, 2006·19 cites·54 claims
- 2271US7222318B2Circuit optimization for minimum path timing violationsSEQUENCE DESIGN INC·Filed 2003·Granted May 22, 2007·13 cites·12 claims
- 2363US7185300B2Vectorless instantaneous current estimationSEQUENCE DESIGN INC·Filed 2004·Granted Feb 27, 2007·8 cites·29 claims
- 2457US6519755B1Method and apparatus for logic synthesis with elaborationSEQUENCE DESIGN INC·Filed 1999·Granted Feb 11, 2003·30 cites·12 claims
- 2538US6493648B1Method and apparatus for logic synthesis (inferring complex components)SEQUENCE DESIGN INC·Filed 1999·Granted Dec 10, 2002·10 cites·12 claims
- 2630US6311312B1Method for modeling a conductive semiconductor substrateSEQUENCE DESIGN INC·Filed 1999·Granted Oct 30, 2001·2 cites·14 claims
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →