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SIFIVE INC

US93 patents

Top patents by PatentIndex Score

US10922462B1Feb 16, 2021

Intellectual property block validation and design integration for integrated circuits

SIFIVE INC42 citations95

USD879730SMar 31, 2020

Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

SIFIVE INC0 citations61

US11687455B2Jun 27, 2023

Data cache with hybrid writeback and writethrough

SIFIVE INC0 citations61

US11467961B2Oct 11, 2022

Data cache with hybrid writeback and writethrough

SIFIVE INC0 citations61

US11301251B2Apr 12, 2022

Fetch stage handling of indirect jumps in a processor pipeline

SIFIVE INC0 citations61

US11048515B2Jun 29, 2021

Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

SIFIVE INC0 citations61

US10996952B2May 4, 2021

Macro-op fusion

SIFIVE INC1 citations61

US12566606B2Mar 3, 2026

Prefetching cache blocks based on an address for a group and a bit field

SIFIVE INC0 citations60

US12554650B2Feb 17, 2026

Store-to-load forwarding for processor pipelines

SIFIVE INC0 citations60

US12487829B2Dec 2, 2025

Macro-op fusion for pipelined architectures

SIFIVE INC0 citations60

US12386764B2Aug 12, 2025

Selective transfer of data including a priority byte

SIFIVE INC0 citations60

US12332799B2Jun 17, 2025

Speculative request indicator in request message

SIFIVE INC0 citations60

US12314718B2May 27, 2025

Stalling issue queue entries until consecutive allocated entries are available for segmented stores

SIFIVE INC0 citations60

US12265829B2Apr 1, 2025

Re-triggering wake-up to handle time skew between scalar and vector sides

SIFIVE INC0 citations60

US12260217B2Mar 25, 2025

Using renamed registers to support multiple vset{i}vl{i} instructions

SIFIVE INC0 citations60

US12248401B2Mar 11, 2025

Eviction operations based on eviction message types of different priorities

SIFIVE INC0 citations60

US12210874B2Jan 28, 2025

Processing for vector load or store micro-operation with inactive mask elements

SIFIVE INC0 citations60

US12204462B2Jan 21, 2025

Downgrading a permission associated with data stored in a cache

SIFIVE INC0 citations60

US12197335B2Jan 14, 2025

Canceling prefetch of cache blocks based on an address and a bit field

SIFIVE INC0 citations60

US12189544B2Jan 7, 2025

Transmitting a response with a request and state information about the request

SIFIVE INC0 citations60

US11847060B2Dec 19, 2023

Data cache with prediction hints for cache hits

SIFIVE INC0 citations60

US11675945B2Jun 13, 2023

Reset crossing and clock crossing interface for integrated circuit generation

SIFIVE INC1 citations60

US11620229B2Apr 4, 2023

Data cache with prediction hints for cache hits

SIFIVE INC0 citations60

US12524352B2Jan 13, 2026

Cache replacement policy state structure with extra states for prefetch and non-temporal loads

SIFIVE INC0 citations59

US12493465B2Dec 9, 2025

Vector load store operations in a vector pipeline using a single operation in a load store unit

SIFIVE INC0 citations59

US12399721B2Aug 26, 2025

Debug in system on a chip with securely partitioned memory space

SIFIVE INC0 citations59

US12332733B2Jun 17, 2025

Determining an error handling mode

SIFIVE INC0 citations59

US12293192B2May 6, 2025

Bundling and dynamic allocation of register blocks for vector instructions

SIFIVE INC0 citations59

US12204458B1Jan 21, 2025

Translation lookaside buffer probing prevention

SIFIVE INC0 citations59

Showing the top 50 of 93 patents by PatentIndex Score.

SIFIVE INC

Top patents by PatentIndex Score

Intellectual property block validation and design integration for integrated circuits

Circuit board

Generation of dynamic design flows for integrated circuits

Generation of dynamic design flows for integrated circuits

Data cache with hybrid writeback and writethrough

Circuit board

Reset crossing and clock crossing interface for integrated circuit generation

Low-swing Schmitt triggers

Pad ring generation for integrated circuits

Zero static high-speed, low power level shifter

Cross-coupled high-speed, low power level shifter

Clock crossing interface for integrated circuit generation

Generation of dynamic design flows for integrated circuits

Virtualized caches

Relative age tracking for entries in a buffer

Duplicate detection for register renaming

Virtualized caches

Duplicate detection for register renaming

Vector instruction processing after primary decode

Load-store pipeline selection for vectors

Macro-op fusion

Fetch stage handling of indirect jumps in a processor pipeline

Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

Data cache with hybrid writeback and writethrough

Data cache with hybrid writeback and writethrough

Fetch stage handling of indirect jumps in a processor pipeline

Way predictor and enable logic for instruction tightly-coupled memory and instruction cache

Macro-op fusion

Prefetching cache blocks based on an address for a group and a bit field

Store-to-load forwarding for processor pipelines

Macro-op fusion for pipelined architectures

Selective transfer of data including a priority byte

Speculative request indicator in request message

Stalling issue queue entries until consecutive allocated entries are available for segmented stores

Re-triggering wake-up to handle time skew between scalar and vector sides

Using renamed registers to support multiple vset{i}vl{i} instructions

Eviction operations based on eviction message types of different priorities

Processing for vector load or store micro-operation with inactive mask elements

Downgrading a permission associated with data stored in a cache

Canceling prefetch of cache blocks based on an address and a bit field

Transmitting a response with a request and state information about the request

Data cache with prediction hints for cache hits

Reset crossing and clock crossing interface for integrated circuit generation

Data cache with prediction hints for cache hits

Cache replacement policy state structure with extra states for prefetch and non-temporal loads

Vector load store operations in a vector pipeline using a single operation in a load store unit

Debug in system on a chip with securely partitioned memory space

Determining an error handling mode

Bundling and dynamic allocation of register blocks for vector instructions

Translation lookaside buffer probing prevention