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US15 patents

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US7257129B2Aug 14, 2007

Memory architecture with multiple serial communications ports

SILICON IMAGE67 citations98
US7154905B2Dec 26, 2006

Method and system for nesting of communications packets

SILICON IMAGE25 citations96
US6693985B2Feb 17, 2004

Clock and data recovery method and apparatus

SILICON IMAGE67 citations96
US6717478B1Apr 6, 2004

Multi-phase voltage controlled oscillator (VCO) with common mode control

SILICON IMAGE70 citations95
US6714206B1Mar 30, 2004

Method and system for spatial-temporal dithering for displays with overlapping pixels

SILICON IMAGE167 citations95
US7103013B1Sep 5, 2006

Bidirectional bridge circuit having high common mode rejection and high input sensitivity

SILICON IMAGE24 citations93
US6985005B1Jan 10, 2006

Differential amplifiers using asymmetric transfer characteristics to suppress input noise in output logic signals

SILICON IMAGE16 citations93
US7113507B2Sep 26, 2006

Method and system for communicating control information via out-of-band symbols

SILICON IMAGE14 citations92
US7027099B2Apr 11, 2006

Method and apparatus for deinterlacing digital video images

SILICON IMAGE35 citations92
US6976201B2Dec 13, 2005

Method and system for host handling of communications errors

SILICON IMAGE22 citations92
US6809567B1Oct 26, 2004

System and method for multiple-phase clock generation

SILICON IMAGE24 citations92
US7109958B1Sep 19, 2006

Supporting circuitry and method for controlling pixels

SILICON IMAGE12 citations84
US7058121B1Jun 6, 2006

Logic gates including diode-connected metal-oxide-semiconductor field-effect transistors (MOSFETS) to control input threshold voltage levels and switching transients of output logic signals

SILICON IMAGE13 citations84
US7039121B2May 2, 2006

Method and system for transition-controlled selective block inversion communications

SILICON IMAGE6 citations73
US7599316B2Oct 6, 2009

Bi-directional bridge circuit having high common mode rejection and high input sensitivity

SILICON IMAGE4 citations63