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SYNOPSYS INC

US2,017 patents

Top patents by PatentIndex Score

US7960232B2Jun 14, 2011

Methods of designing an integrated circuit on corrugated substrate

SYNOPSYS INC139 citations99

US7528465B2May 5, 2009

Integrated circuit on corrugated substrate

SYNOPSYS INC347 citations99

US7509621B2Mar 24, 2009

Method and apparatus for placing assist features by identifying locations of constructive and destructive interference

SYNOPSYS INC222 citations99

US7265008B2Sep 4, 2007

Dissection of printed edges from a fabrication layout for correcting proximity effects

SYNOPSYS INC215 citations99

US6438729B1Aug 20, 2002

Connectivity-based approach for extracting layout parasitics

SYNOPSYS INC116 citations99

US6378110B1Apr 23, 2002

Layer-based rule checking for an integrated circuit layout

SYNOPSYS INC273 citations99

US5903469AMay 11, 1999

Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

SYNOPSYS INC140 citations99

US7926018B2Apr 12, 2011

Method and apparatus for generating a layout for a transistor

SYNOPSYS INC108 citations98

US7895548B2Feb 22, 2011

Filler cells for design optimization in a place-and-route system

SYNOPSYS INC128 citations98

US7605449B2Oct 20, 2009

Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material

SYNOPSYS INC336 citations98

US7508031B2Mar 24, 2009

Enhanced segmented channel MOS transistor with narrowed base regions

SYNOPSYS INC343 citations98

US7509622B2Mar 24, 2009

Dummy filling technique for improved planarization of chip surface topography

SYNOPSYS INC243 citations98

US7312003B2Dec 25, 2007

Design and layout of phase shifting photolithographic masks

SYNOPSYS INC116 citations98

US7237162B1Jun 26, 2007

Deterministic BIST architecture tolerant of uncertain scan chain outputs

SYNOPSYS INC69 citations98

US7122281B2Oct 17, 2006

Critical dimension control using full phase and trim masks

SYNOPSYS INC142 citations98

US7028285B2Apr 11, 2006

Standard cell design incorporating phase information

SYNOPSYS INC262 citations98

US6978436B2Dec 20, 2005

Design data format and hierarchy management for phase processing

SYNOPSYS INC207 citations98

US6950974B1Sep 27, 2005

Efficient compression and application of deterministic patterns in a logic BIST architecture

SYNOPSYS INC92 citations98

US6873720B2Mar 29, 2005

System and method of providing mask defect printability analysis

SYNOPSYS INC112 citations98

US6615380B1Sep 2, 2003

Dynamic scan chains and test pattern generation methodologies therefor

SYNOPSYS INC91 citations98

US5778169AJul 7, 1998

Computer system having improved regression testing

SYNOPSYS INC115 citations98

US7827510B1Nov 2, 2010

Enhanced hardware debugging with embedded FPGAS in a hardware description language

SYNOPSYS INC88 citations97

US7454731B2Nov 18, 2008

Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques

SYNOPSYS INC216 citations97

US7421678B2Sep 2, 2008

Assist feature placement using a process-sensitivity model

SYNOPSYS INC200 citations97

US7107571B2Sep 12, 2006

Visual analysis and verification system using advanced tools

SYNOPSYS INC87 citations97

US6928635B2Aug 9, 2005

Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits

SYNOPSYS INC236 citations97

US6449755B1Sep 10, 2002

Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

SYNOPSYS INC88 citations97

US6385750B1May 7, 2002

Method and system for controlling test data volume in deterministic test pattern generation

SYNOPSYS INC97 citations97

US6345379B1Feb 5, 2002

Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist

SYNOPSYS INC123 citations97

US6311317B1Oct 30, 2001

Pre-synthesis test point insertion

SYNOPSYS INC91 citations97

US6075932AJun 13, 2000

Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist

SYNOPSYS INC93 citations97

US6011911AJan 4, 2000

Layout overlap detection with selective flattening in computer implemented integrated circuit design

SYNOPSYS INC198 citations97

US6009251ADec 28, 1999

Method and system for layout verification of an integrated circuit design with reusable subdesigns

SYNOPSYS INC454 citations97

US5903466AMay 11, 1999

Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design

SYNOPSYS INC162 citations97

US5828579AOct 27, 1998

Scan segment processing within hierarchical scan architecture for design for test applications

SYNOPSYS INC100 citations97

US5754826AMay 19, 1998

CAD and simulation system for targeting IC designs to multiple fabrication processes

SYNOPSYS INC374 citations97

US5696694ADec 9, 1997

Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist

SYNOPSYS INC114 citations97

US5696771ADec 9, 1997

Method and apparatus for performing partial unscan and near full scan within design for test applications

SYNOPSYS INC112 citations97

US7739624B2Jun 15, 2010

Methods and apparatuses to generate a shielding mesh for integrated circuit devices

SYNOPSYS INC27 citations96

US7484198B2Jan 27, 2009

Managing integrated circuit stress using dummy diffusion regions

SYNOPSYS INC48 citations96

US7093229B2Aug 15, 2006

System and method for providing defect printability analysis of photolithographic masks with job-based automation

SYNOPSYS INC54 citations96

US6993694B1Jan 31, 2006

Deterministic bist architecture including MISR filter

SYNOPSYS INC75 citations96

US6961689B1Nov 1, 2005

Scheduling non-integral simulation time for mixed-signal simulation

SYNOPSYS INC155 citations96

US6807646B1Oct 19, 2004

System and method for time slicing deterministic patterns for reseeding in logic built-in self-test

SYNOPSYS INC61 citations96

US6539536B1Mar 25, 2003

Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics

SYNOPSYS INC185 citations96

Showing the top 50 of 2,017 patents by PatentIndex Score.

SYNOPSYS INC

Top patents by PatentIndex Score

Methods of designing an integrated circuit on corrugated substrate

Integrated circuit on corrugated substrate

Method and apparatus for placing assist features by identifying locations of constructive and destructive interference

Method of IC production using corrugated substrate

Segmented channel MOS transistor

Integrated circuit on corrugated substrate

Phase shift masking for complex patterns with proximity adjustments

High yield reticle with proximity effect halos

Dissection of printed edges from a fabrication layout for correcting proximity effects

Connectivity-based approach for extracting layout parasitics

Layer-based rule checking for an integrated circuit layout

Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

Method and apparatus for generating a layout for a transistor

Filler cells for design optimization in a place-and-route system

Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material

Enhanced segmented channel MOS transistor with narrowed base regions

Dummy filling technique for improved planarization of chip surface topography

Design and layout of phase shifting photolithographic masks

Deterministic BIST architecture tolerant of uncertain scan chain outputs

Critical dimension control using full phase and trim masks

Standard cell design incorporating phase information

Design data format and hierarchy management for phase processing

Efficient compression and application of deterministic patterns in a logic BIST architecture

System and method of providing mask defect printability analysis

Dynamic scan chains and test pattern generation methodologies therefor

Computer system having improved regression testing

Enhanced hardware debugging with embedded FPGAS in a hardware description language

Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques

Assist feature placement using a process-sensitivity model

Visual analysis and verification system using advanced tools

Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits

Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

Method and system for controlling test data volume in deterministic test pattern generation

Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist

Pre-synthesis test point insertion

Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist

Layout overlap detection with selective flattening in computer implemented integrated circuit design

Method and system for layout verification of an integrated circuit design with reusable subdesigns

Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design

Scan segment processing within hierarchical scan architecture for design for test applications

CAD and simulation system for targeting IC designs to multiple fabrication processes

Method and apparatus for estimating internal power consumption of an electronic circuit represented as netlist

Method and apparatus for performing partial unscan and near full scan within design for test applications

Methods and apparatuses to generate a shielding mesh for integrated circuit devices

Managing integrated circuit stress using dummy diffusion regions

System and method for providing defect printability analysis of photolithographic masks with job-based automation

Deterministic bist architecture including MISR filter

Scheduling non-integral simulation time for mixed-signal simulation

System and method for time slicing deterministic patterns for reseeding in logic built-in self-test

Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristics