Assignee
SYNTEST TECHNOLOGIES INC
US·44 granted patents·2 pending applications·955 citations·filing 2002–2015
Top patents by PatentIndex Score
46 records- 0197US7412637B2Method and apparatus for broadcasting test patterns in a scan based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Aug 12, 2008·62 cites·86 claims
- 0296US7412672B1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 12, 2008·36 cites·58 claims
- 0396US7058869B2Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Jun 6, 2006·119 cites·34 claims
- 0495US7925947B1X-canceling multiple-input signature register (MISR) for compacting output responses with unknownsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Apr 12, 2011·36 cites·20 claims
- 0595US7032148B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Apr 18, 2006·84 cites·76 claims
- 0694US7284175B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Oct 16, 2007·30 cites·27 claims
- 0794US6954887B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 11, 2005·64 cites·33 claims
- 0893US8775985B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 8, 2014·7 cites·2 claims
- 0993US7945833B1Method and apparatus for pipelined scan compressionSYNTEST TECHNOLOGIES INC·Filed 2007·Granted May 17, 2011·29 cites·34 claims
- 1093US7007213B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Feb 28, 2006·52 cites·30 claims
- 1193US6957403B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Oct 18, 2005·69 cites·68 claims
- 1292US7904857B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Mar 8, 2011·20 cites·12 claims
- 1391US7191373B2Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniquesSYNTEST TECHNOLOGIES INC·Filed 2002·Granted Mar 13, 2007·48 cites·19 claims
- 1490US9046572B2Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faultsSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jun 2, 2015·6 cites·32 claims
- 1590US7231570B2Method and apparatus for multi-level scan compressionSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Jun 12, 2007·21 cites·30 claims
- 1688US7331032B2Computer-aided design system to automate scan synthesis at register-transfer levelSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Feb 12, 2008·12 cites·11 claims
- 1787US9110139B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2014·Granted Aug 18, 2015·4 cites·21 claims
- 1887US7945830B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2010·Granted May 17, 2011·5 cites·30 claims
- 1987US7512851B2Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Mar 31, 2009·39 cites·46 claims
- 2087US7210082B1Method for performing ATPG and fault simulation in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Apr 24, 2007·16 cites·10 claims
- 2186US7996741B2Method and apparatus for low-pin-count scan compressionSYNTEST TECHNOLOGIES INC·Filed 2009·Granted Aug 9, 2011·11 cites·46 claims
- 2286US7552373B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Jun 23, 2009·36 cites·44 claims
- 2386US7260756B1Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 21, 2007·11 cites·79 claims
- 2485US7721172B2Method and apparatus for broadcasting test patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2008·Granted May 18, 2010·11 cites·26 claims
- 2584US9121902B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2014·Granted Sep 1, 2015·3 cites·30 claims
- 2684US7124342B2Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Oct 17, 2006·31 cites·102 claims
- 2783US7779322B1Compacting test responses using X-driven compactorSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Aug 17, 2010·12 cites·12 claims
- 2883US7590905B2Method and apparatus for pipelined scan compressionSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Sep 15, 2009·13 cites·40 claims
- 2982US7451371B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Nov 11, 2008·9 cites·33 claims
- 3082US7434126B2Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faultsSYNTEST TECHNOLOGIES INC·Filed 2007·Granted Oct 7, 2008·8 cites·7 claims
- 3181US7747920B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Jun 29, 2010·8 cites·24 claims
- 3279US7735049B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2006·Granted Jun 8, 2010·8 cites·38 claims
- 3378US7444567B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Oct 28, 2008·17 cites·18 claims
- 3476US9057763B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jun 16, 2015·2 cites·98 claims
- 3576US9026875B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted May 5, 2015·2 cites·55 claims
- 3675US7779323B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Aug 17, 2010·5 cites·21 claims
- 3768US8769359B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 1, 2014·1 cites·30 claims
- 3868US7904773B2Multiple-capture DFT system for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Mar 8, 2011·4 cites·34 claims
- 3959US9316688B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2015·Granted Apr 19, 2016·0 cites·36 claims
- 4059US9274168B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2015·Granted Mar 1, 2016·0 cites·30 claims
- 4159US7721173B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2009·Granted May 18, 2010·3 cites·47 claims
- 4257US9091730B2Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-testSYNTEST TECHNOLOGIES INC·Filed 2013·Granted Jul 28, 2015·0 cites·84 claims
- 4349US7228479B2IEEE Std. 1149.4 compatible analog BIST methodologySYNTEST TECHNOLOGIES INC·Filed 2005·Granted Jun 5, 2007·1 cites·14 claims
- 4447US2008276141A1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
- 4541US2013326281A1X-Tracer: A Reconfigurable X-Tolerance Trace Compressor for Silicon DebugSYNTEST TECHNOLOGIES INC·Filed 2013·Application pending·0 cites
- 4636US7783940B2Apparatus for redundancy reconfiguration of faculty memoriesSYNTEST TECHNOLOGIES INC·Filed 2008·Granted Aug 24, 2010·0 cites·5 claims
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