Assignee
TANZAWA TORU
JP·35 granted patents·2 pending applications·320 citations·filing 2005–2012
Top patents by PatentIndex Score
37 records- 0197US8860117B2Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methodsTANZAWA TORU·Filed 2011·Granted Oct 14, 2014·21 cites·30 claims
- 0297US8619471B2Apparatuses and methods including memory array data line selectionTANZAWA TORU·Filed 2011·Granted Dec 31, 2013·30 cites·46 claims
- 0396US9111620B2Memory having memory cell string and coupling componentsTANZAWA TORU·Filed 2012·Granted Aug 18, 2015·17 cites·25 claims
- 0496US8976594B2Memory read apparatus and methodsTANZAWA TORU·Filed 2012·Granted Mar 10, 2015·19 cites·23 claims
- 0595US8811084B2Memory array with power-efficient read architectureTANZAWA TORU·Filed 2012·Granted Aug 19, 2014·15 cites·32 claims
- 0694US8837222B2Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrateTANZAWA TORU·Filed 2011·Granted Sep 16, 2014·11 cites·20 claims
- 0793US8593869B2Apparatuses and methods including memory array and data line architectureTANZAWA TORU·Filed 2011·Granted Nov 26, 2013·15 cites·48 claims
- 0892US9595533B2Memory array having connections going through control gatesTANZAWA TORU·Filed 2012·Granted Mar 14, 2017·14 cites·11 claims
- 0992US8796778B2Apparatuses and methods for transposing select gatesTANZAWA TORU·Filed 2011·Granted Aug 5, 2014·11 cites·39 claims
- 1092US8797804B2Vertical memory with body connectionTANZAWA TORU·Filed 2012·Granted Aug 5, 2014·13 cites·15 claims
- 1192US8184489B2Level shifting circuitTANZAWA TORU·Filed 2010·Granted May 22, 2012·10 cites·25 claims
- 1291US8952482B2Three-dimensional devices having reduced contact lengthTANZAWA TORU·Filed 2012·Granted Feb 10, 2015·8 cites·15 claims
- 1391US8547746B2Voltage generation and adjustment in a memory deviceTANZAWA TORU·Filed 2011·Granted Oct 1, 2013·12 cites·45 claims
- 1490US8891305B2Apparatuses and methods involving accessing distributed sub-blocks of memory cellsTANZAWA TORU·Filed 2012·Granted Nov 18, 2014·8 cites·29 claims
- 1590US8792263B2Apparatuses and methods including memory with top and bottom data linesTANZAWA TORU·Filed 2011·Granted Jul 29, 2014·11 cites·26 claims
- 1690US8780631B2Memory devices having data lines included in top and bottom conductive linesTANZAWA TORU·Filed 2012·Granted Jul 15, 2014·11 cites·12 claims
- 1789US9064551B2Apparatuses and methods for coupling load current to a common sourceTANZAWA TORU·Filed 2012·Granted Jun 23, 2015·10 cites·23 claims
- 1889US8253396B2Voltage regulator systemTANZAWA TORU·Filed 2011·Granted Aug 28, 2012·10 cites·20 claims
- 1989US8208305B2Arrangement of pairs of NAND strings that share bitline contacts while utilizing distinct sources linesTANZAWA TORU·Filed 2009·Granted Jun 26, 2012·21 cites·26 claims
- 2085US8125829B2Biasing system and methodTANZAWA TORU·Filed 2008·Granted Feb 28, 2012·12 cites·16 claims
- 2181US8611153B2Biasing system and methodTANZAWA TORU·Filed 2012·Granted Dec 17, 2013·5 cites·27 claims
- 2279US9042180B2Charge pump redundancy in a memoryTANZAWA TORU·Filed 2012·Granted May 26, 2015·6 cites·25 claims
- 2379US8743622B2Memory devices and programming methods that program a memory cell with a data value, read the data value from the memory cell and reprogram the memory cell with the read data valueTANZAWA TORU·Filed 2012·Granted Jun 3, 2014·5 cites·33 claims
- 2478US8466664B2Voltage trimmingTANZAWA TORU·Filed 2011·Granted Jun 18, 2013·5 cites·29 claims
- 2578US8446784B2Level shifting circuitTANZAWA TORU·Filed 2012·Granted May 21, 2013·5 cites·22 claims
- 2675US8971117B2Apparatus and methods for applying a non-zero voltage differential across a memory cell not involved in an access operationTANZAWA TORU·Filed 2012·Granted Mar 3, 2015·4 cites·39 claims
- 2775US8681561B2Apparatuses and methods including memory write operationTANZAWA TORU·Filed 2011·Granted Mar 25, 2014·4 cites·41 claims
- 2867US8253198B2Devices for shielding a signal line over an active regionTANZAWA TORU·Filed 2009·Granted Aug 28, 2012·2 cites·26 claims
- 2957US9000836B2Voltage generator circuitTANZAWA TORU·Filed 2008·Granted Apr 7, 2015·3 cites·28 claims
- 3057US8861274B2Compensating for off-current in a memoryTANZAWA TORU·Filed 2012·Granted Oct 14, 2014·1 cites·29 claims
- 3155US8675420B2Devices and systems including enabling circuitsTANZAWA TORU·Filed 2011·Granted Mar 18, 2014·1 cites·26 claims
- 3254US8853778B2Devices for shielding a signal line over an active regionTANZAWA TORU·Filed 2012·Granted Oct 7, 2014·0 cites·19 claims
- 3352US8537620B2Random telegraph signal noise reduction scheme for semiconductor memoriesTANZAWA TORU·Filed 2012·Granted Sep 17, 2013·0 cites·26 claims
- 3451US8194459B2Random telegraph signal noise reduction scheme for semiconductor memoriesTANZAWA TORU·Filed 2011·Granted Jun 5, 2012·0 cites·26 claims
- 3543US9727417B2Chunk redundancy architecture for memoryTANZAWA TORU·Filed 2012·Granted Aug 8, 2017·0 cites·16 claims
- 3638US2007046363A1Method and apparatus for generating a variable output voltage from a bandgap referenceTANZAWA TORU·Filed 2005·Application pending·0 cites
- 3737US2007046341A1Method and apparatus for generating a power on reset with a low temperature coefficientTANZAWA TORU·Filed 2005·Application pending·0 cites
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