Assignee
TELA INNOVATIONS INC
US·105 granted patents·19 pending applications·4,105 citations·filing 2005–2020
Top patents by PatentIndex Score
124 records- 0199US9443947B2Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Sep 13, 2016·28 cites·30 claims
- 0299US9425273B2Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Aug 23, 2016·24 cites·30 claims
- 0399US9425272B2Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Aug 23, 2016·24 cites·30 claims
- 0499US8836045B2Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode trackTELA INNOVATIONS INC·Filed 2013·Granted Sep 16, 2014·57 cites·25 claims
- 0599US8701071B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2013·Granted Apr 15, 2014·64 cites·20 claims
- 0699US8356268B2Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacingsTELA INNOVATIONS INC·Filed 2011·Granted Jan 15, 2013·129 cites·29 claims
- 0799US8035133B2Semiconductor device having two pairs of transistors of different types formed from shared linear-shaped conductive features with intervening transistors of common type on equal pitchTELA INNOVATIONS INC·Filed 2009·Granted Oct 11, 2011·108 cites·38 claims
- 0899US8030689B2Integrated circuit device and associated layout including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear conductive segmentTELA INNOVATIONS INC·Filed 2009·Granted Oct 4, 2011·112 cites·46 claims
- 0999US8022441B2Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect levelTELA INNOVATIONS INC·Filed 2009·Granted Sep 20, 2011·108 cites·34 claims
- 1099US7989848B2Semiconductor device having at least four side-by-side electrodes of equal length and equal pitch with at least two transistor connections to power or groundTELA INNOVATIONS INC·Filed 2009·Granted Aug 2, 2011·107 cites·33 claims
- 1199US7989847B2Semiconductor device having linear-shaped gate electrodes of different transistor types with uniformity extending portions of different lengthsTELA INNOVATIONS INC·Filed 2009·Granted Aug 2, 2011·108 cites·38 claims
- 1299US7956421B2Cross-coupled transistor layouts in restricted gate level layout architectureTELA INNOVATIONS INC·Filed 2009·Granted Jun 7, 2011·144 cites·37 claims
- 1399US7952119B2Semiconductor device and associated layout having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitchTELA INNOVATIONS INC·Filed 2009·Granted May 31, 2011·111 cites·37 claims
- 1499US7948012B2Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segmentTELA INNOVATIONS INC·Filed 2009·Granted May 24, 2011·107 cites·35 claims
- 1599US7948013B2Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitchTELA INNOVATIONS INC·Filed 2009·Granted May 24, 2011·107 cites·25 claims
- 1699US7943966B2Integrated circuit and associated layout with gate electrode level portion including at least two complimentary transistor forming linear conductive segments and at least one non-gate linear conductive segmentTELA INNOVATIONS INC·Filed 2009·Granted May 17, 2011·116 cites·35 claims
- 1799US7943967B2Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segmentsTELA INNOVATIONS INC·Filed 2009·Granted May 17, 2011·114 cites·36 claims
- 1899US7932545B2Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometersTELA INNOVATIONS INC·Filed 2009·Granted Apr 26, 2011·145 cites·33 claims
- 1999US7932544B2Semiconductor device and associated layouts including linear conductive segments having non-gate extension portionsTELA INNOVATIONS INC·Filed 2009·Granted Apr 26, 2011·109 cites·31 claims
- 2099US7923757B2Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect levelTELA INNOVATIONS INC·Filed 2009·Granted Apr 12, 2011·112 cites·34 claims
- 2199US7917879B2Semiconductor device with dynamic array sectionTELA INNOVATIONS INC·Filed 2008·Granted Mar 29, 2011·158 cites·25 claims
- 2299US7910959B2Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect levelTELA INNOVATIONS INC·Filed 2009·Granted Mar 22, 2011·111 cites·33 claims
- 2399US7910958B2Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segmentTELA INNOVATIONS INC·Filed 2009·Granted Mar 22, 2011·149 cites·35 claims
- 2499US7908578B2Methods for designing semiconductor device with dynamic array sectionTELA INNOVATIONS INC·Filed 2008·Granted Mar 15, 2011·152 cites·25 claims
- 2599US7906801B2Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictionsTELA INNOVATIONS INC·Filed 2009·Granted Mar 15, 2011·115 cites·30 claims
- 2699US7888705B2Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the sameTELA INNOVATIONS INC·Filed 2008·Granted Feb 15, 2011·165 cites·22 claims
- 2799US7842975B2Dynamic array architectureTELA INNOVATIONS INC·Filed 2008·Granted Nov 30, 2010·150 cites·31 claims
- 2899US7446352B2Dynamic array architectureTELA INNOVATIONS INC·Filed 2007·Granted Nov 4, 2008·254 cites·31 claims
- 2998US9905576B2Semiconductor chip including region having rectangular-shaped gate structures and first metal structuresTELA INNOVATIONS INC·Filed 2017·Granted Feb 27, 2018·8 cites·30 claims
- 3098US9336344B2Coarse grid design methods and structuresTELA INNOVATIONS INC·Filed 2014·Granted May 10, 2016·38 cites·22 claims
- 3198US9202779B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2014·Granted Dec 1, 2015·42 cites·21 claims
- 3298US8921896B2Integrated circuit including linear gate electrode structures having different extension distances beyond contactTELA INNOVATIONS INC·Filed 2013·Granted Dec 30, 2014·18 cites·48 claims
- 3398US8853794B2Integrated circuit within semiconductor chip including cross-coupled transistor configurationTELA INNOVATIONS INC·Filed 2014·Granted Oct 7, 2014·16 cites·30 claims
- 3498US7917885B2Methods for creating primitive constructed standard cellsTELA INNOVATIONS INC·Filed 2008·Granted Mar 29, 2011·92 cites·27 claims
- 3598US7640522B2Method and system for placing layout objects in a standard-cell layoutTELA INNOVATIONS INC·Filed 2006·Granted Dec 29, 2009·110 cites·42 claims
- 3697US8946781B2Integrated circuit including gate electrode conductive structures with different extension distances beyond contactTELA INNOVATIONS INC·Filed 2013·Granted Feb 3, 2015·11 cites·48 claims
- 3797US7939443B2Methods for multi-wire routing and apparatus implementing sameTELA INNOVATIONS INC·Filed 2009·Granted May 10, 2011·56 cites·28 claims
- 3896US10217763B2Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical gridTELA INNOVATIONS INC·Filed 2018·Granted Feb 26, 2019·4 cites·28 claims
- 3996US9917056B2Coarse grid design methods and structuresTELA INNOVATIONS INC·Filed 2016·Granted Mar 13, 2018·10 cites·26 claims
- 4096US9633987B2Integrated circuit cell library for multiple patterningTELA INNOVATIONS INC·Filed 2014·Granted Apr 25, 2017·28 cites·20 claims
- 4196US9213792B2Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methodsTELA INNOVATIONS INC·Filed 2015·Granted Dec 15, 2015·7 cites·30 claims
- 4296US8823062B2Integrated circuit with offset line end spacings in linear gate electrode levelTELA INNOVATIONS INC·Filed 2013·Granted Sep 2, 2014·8 cites·49 claims
- 4396US7743349B2Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuitTELA INNOVATIONS INC·Filed 2005·Granted Jun 22, 2010·28 cites·13 claims
- 4495US9035359B2Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methodsTELA INNOVATIONS INC·Filed 2014·Granted May 19, 2015·34 cites·30 claims
- 4595US7763534B2Methods, structures and designs for self-aligning local interconnects used in integrated circuitsTELA INNOVATIONS INC·Filed 2008·Granted Jul 27, 2010·22 cites·19 claims
- 4694US8952425B2Integrated circuit including at least four linear-shaped conductive structures having extending portions of different lengthTELA INNOVATIONS INC·Filed 2013·Granted Feb 10, 2015·6 cites·38 claims
- 4794US8921897B2Integrated circuit with gate electrode conductive structures having offset endsTELA INNOVATIONS INC·Filed 2013·Granted Dec 30, 2014·6 cites·49 claims
- 4894US8847331B2Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structuresTELA INNOVATIONS INC·Filed 2014·Granted Sep 30, 2014·6 cites·30 claims
- 4993US9536899B2Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Jan 3, 2017·4 cites·30 claims
- 5093US8872283B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level featureTELA INNOVATIONS INC·Filed 2013·Granted Oct 28, 2014·6 cites·24 claims
Showing the top 50 of 124 patent records by PatentIndex Score.
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