Assignee
TENSTORRENT USA INC
US·5 granted patents·27 pending applications·0 citations·filing 2024–2025
Top patents by PatentIndex Score
32 records- 0172US2026077772A1Distributed Subsystems with Embedded AI Compute in an Automotive SystemTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 0270US2025383881A1Processor with Opportunistic Bypass of Dispatch Buffer and Reservation StationTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 0367US12430137B1Processor with opportunistic bypass of dispatch buffer and reservation stationTENSTORRENT USA INC·Filed 2024·Granted Sep 30, 2025·0 cites·14 claims
- 0465US12423111B1Static instruction caching in a coprocessor architectureTENSTORRENT USA INC·Filed 2024·Granted Sep 23, 2025·0 cites·20 claims
- 0563US2026064500A1Time division multiplexing shared memoryTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 0662US12572379B2Static trusted execution environment for inter-architecture processor program compatibilityTENSTORRENT USA INC·Filed 2024·Granted Mar 10, 2026·0 cites·23 claims
- 0762US2025322948A1Efficient compression instruction handling in a processing pipelineTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 0861US2026090392A1Chip-to-Chip High Speed Connection Interface Tuning StructureTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 0960US2026064417A1Processor with descriptor table instruction circuitryTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 1058US2025306624A1Multicore Processor Clock Distribution Using Asynchronous WavefrontTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 1158US2025298429A1Multi-Level Critical Temperature Protection and Workload Efficiency Resilience for a Computer ProcessorTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 1256US12517732B2Processor with one or more progressive conservative execution modesTENSTORRENT USA INC·Filed 2024·Granted Jan 6, 2026·0 cites·30 claims
- 1356US2025310250A1Classification Engine with Field Reduction for Ethernet RoutingTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 1456US2025298511A1Memory status based traffic routing on heterogeneous memory subsystemTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 1555US12572357B2Vector mask buffers in a vector instruction execution pipelineTENSTORRENT USA INC·Filed 2024·Granted Mar 10, 2026·0 cites·25 claims
- 1655US2025307197A1AI Accelerator Cores with Integrated CPU for External Communication Over EthernetTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 1755US2025298672A1Flexible Cache Pooling for Network of Processing CoresTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 1854US2025286747A1Network-on-Chip Multicasting with Packet Specific Exclusion EncodingTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 1953US2026023565A1Adaptive memory address computation based on tensor dimensionsTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2052US2025307345A1Integrated Heterogeneous Processing Cores for Unified Independent Computation ExecutionTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2152US2025252075A1Network on Chip with Data Movement Processing CoresTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2252US2026023913A1Area-efficient functional safety in computer processing unitsTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 2352US2025251921A1Multicore Processors with Resource Sharing Clusters for AI AccelerationTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2452US2025335363A1Transaction and Request Buffers for Cache Miss HandlingTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2551US2025258770A1Data Identity Based Caching in a Network of Computational NodesTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2651US2025291598A1Instruction fetch group exit point prediction using offset countersTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 2749US2025306931A1Software Managed Cache with Hardware OptimizationTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2847US2025328350A1Branch Status Table and Control Instruction Buffer for Processor Instruction PipelineTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 2947US2025348319A1Instruction Caching Scheme for High Performance RISC ProcessorsTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
- 3047US2025328456A1Window-Based Memory Dependency PredictorTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 3144US2025306932A1Hardware Managed Synchronization of Coprocessor Instruction ExecutionTENSTORRENT USA INC·Filed 2025·Application pending·0 cites
- 3242US2025307014A1Processor with dispatch buffer allocation affinity credit adjustmentTENSTORRENT USA INC·Filed 2024·Application pending·0 cites
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