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TILERA CORP

US29 patents

Top patents by PatentIndex Score

US8050256B1Nov 1, 2011

Configuring routing in mesh networks

TILERA CORP132 citations99
US7882307B1Feb 1, 2011

Managing cache memory in a parallel processing environment

TILERA CORP132 citations99
US7461236B1Dec 2, 2008

Transferring data in a parallel processing environment

TILERA CORP178 citations99
US8045546B1Oct 25, 2011

Configuring routing in mesh networks

TILERA CORP79 citations98
US7853774B1Dec 14, 2010

Managing buffer storage in a parallel processing environment

TILERA CORP59 citations98
US7805575B1Sep 28, 2010

Caching in multicore and multiprocessor architectures

TILERA CORP139 citations98
US7805577B1Sep 28, 2010

Managing memory access in a parallel processing environment

TILERA CORP62 citations98
US7805392B1Sep 28, 2010

Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table

TILERA CORP132 citations98
US7734894B1Jun 8, 2010

Managing data forwarded between processors in a parallel processing environment based on operations associated with instructions issued by the processors

TILERA CORP75 citations98
US7636835B1Dec 22, 2009

Coupling data in a parallel processing environment

TILERA CORP63 citations98
US7620791B1Nov 17, 2009

Mapping memory in a parallel processing environment

TILERA CORP84 citations98
US7577820B1Aug 18, 2009

Managing data in a parallel processing environment

TILERA CORP86 citations98
US7539845B1May 26, 2009

Coupling integrated circuits in a parallel processing environment

TILERA CORP135 citations98
US7461210B1Dec 2, 2008

Managing set associative cache memory according to entry type

TILERA CORP82 citations98
US7853755B1Dec 14, 2010

Caching in multicore and multiprocessor architectures

TILERA CORP56 citations97
US7853754B1Dec 14, 2010

Caching in multicore and multiprocessor architectures

TILERA CORP23 citations96
US7853752B1Dec 14, 2010

Caching in multicore and multiprocessor architectures

TILERA CORP36 citations96
US10210092B1Feb 19, 2019

Managing cache access and streaming data

TILERA CORP16 citations94
US7793074B1Sep 7, 2010

Directing data in a parallel processing environment

TILERA CORP27 citations93
US7774579B1Aug 10, 2010

Protection in a parallel processing environment using access information associated with each switch to prevent data from being forwarded outside a plurality of tiles

TILERA CORP37 citations93
US7624248B1Nov 24, 2009

Managing memory in a parallel processing environment

TILERA CORP29 citations93
US8018849B1Sep 13, 2011

Flow control in a parallel processing environment

TILERA CORP15 citations92
US7987321B1Jul 26, 2011

Caching in multicore and multiprocessor architectures

TILERA CORP16 citations92
US7814242B1Oct 12, 2010

Managing data flows in a parallel processing environment

TILERA CORP13 citations92
US7668979B1Feb 23, 2010

Buffering data in a parallel processing environment

TILERA CORP26 citations92
US7877401B1Jan 25, 2011

Pattern matching

TILERA CORP38 citations91
US7552241B2Jun 23, 2009

Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip

TILERA CORP9 citations84
US9424228B2Aug 23, 2016

High performance, scalable multi chip interconnect

TILERA CORP3 citations73
US7673206B2Mar 2, 2010

Method and system for routing scan chains in an array of processor resources

TILERA CORP3 citations60