Assignee

TSAI CHING-LING

TW·1 granted patent·1 pending application·0 citations·filing 2011–2011

Technology mixG06F1 H10D1

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2 records

0129US8397201B2Method of simulating an ESD circuit layoutTSAI CHING-LING·Filed 2011·Granted Mar 12, 2013·0 cites·11 claims
0225US2013050884A1Electrostatic discharge (esd) protection element and esd circuit thereofTSAI CHING-LING·Filed 2011·Application pending·0 cites

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