Assignee

VLSI TECHNOLOGY CORP

US·1 granted patent·19 citations·filing 1995–1995

Technology mixH05K1 Y02P1 Y10T1

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1 record

0156US5742009APrinted circuit board layout to minimize the clock delay caused by mismatch in length of metal lines and enhance the thermal performance of microeletronics packages via condution through the package leadsVLSI TECHNOLOGY CORP·Filed 1995·Granted Apr 21, 1998·19 cites·8 claims

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