Assignee
WU CHAO-I
TW·11 granted patents·12 citations·filing 2005–2011
Top patents by PatentIndex Score
11 records- 0169US8432745B2High second bit operation window method for virtual ground array with two-bit memory cellsWU CHAO-I·Filed 2011·Granted Apr 30, 2013·2 cites·1 claims
- 0266US8329535B2Multi-level-cell trapping DRAMWU CHAO-I·Filed 2007·Granted Dec 11, 2012·3 cites·13 claims
- 0362US8223540B2Method and apparatus for double-sided biasing of nonvolatile memoryWU CHAO-I·Filed 2007·Granted Jul 17, 2012·2 cites·14 claims
- 0461US8481388B2Non-volatile memory device having a nitride-oxide dielectric layerWU CHAO-I·Filed 2010·Granted Jul 9, 2013·1 cites·10 claims
- 0561US8426906B2Method and structure for a semiconductor charge storage deviceWU CHAO-I·Filed 2008·Granted Apr 23, 2013·2 cites·15 claims
- 0660US8467238B2Dynamic pulse operation for phase change memoryWU CHAO-I·Filed 2010·Granted Jun 18, 2013·2 cites·18 claims
- 0750US8295094B2Method of operating non-volatile memory cellWU CHAO-I·Filed 2011·Granted Oct 23, 2012·0 cites·15 claims
- 0848US8334182B2Method for manufacturing non-volatile memoryWU CHAO-I·Filed 2011·Granted Dec 18, 2012·0 cites·9 claims
- 0948US8263464B2Systems and methods for memory structure comprising a PPROM and an embedded flash memoryWU CHAO I·Filed 2010·Granted Sep 11, 2012·0 cites·13 claims
- 1048US8138540B2Trench type non-volatile memory having three storage locations in one memory cellWU CHAO-I·Filed 2005·Granted Mar 20, 2012·0 cites·16 claims
- 1141US8258029B2Semiconductor structure and process for reducing the second bit effect of a memory deviceWU CHAO-I·Filed 2007·Granted Sep 4, 2012·0 cites·9 claims
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