Assignee
YUAN LEI
US·9 granted patents·2 pending applications·35 citations·filing 2006–2012
Top patents by PatentIndex Score
11 records- 0190US8802574B2Methods of making jogged layout routings double patterning compliantYUAN LEI·Filed 2012·Granted Aug 12, 2014·11 cites·12 claims
- 0281US8765599B2Semiconductor devices having dielectric caps on contacts and related fabrication methodsYUAN LEI·Filed 2012·Granted Jul 1, 2014·5 cites·20 claims
- 0380US8735050B2Integrated circuits and methods for fabricating integrated circuits using double patterning processesYUAN LEI·Filed 2012·Granted May 27, 2014·3 cites·18 claims
- 0479US8677291B1Double patterning compatible colorless M1 routeYUAN LEI·Filed 2012·Granted Mar 18, 2014·6 cites·19 claims
- 0577US8719757B2Method to enhance double patterning routing efficiencyYUAN LEI·Filed 2012·Granted May 6, 2014·4 cites·18 claims
- 0672US9268897B2Method for increasing the robustness of a double patterning router used to manufacture integrated circuit devicesYUAN LEI·Filed 2012·Granted Feb 23, 2016·3 cites·18 claims
- 0771US8809184B2Methods of forming contacts for semiconductor devices using a local interconnect processing schemeYUAN LEI·Filed 2012·Granted Aug 19, 2014·3 cites·14 claims
- 0845US8324106B2Methods for fabricating a photolithographic mask and for fabricating a semiconductor integrated circuit using such a maskYUAN LEI·Filed 2011·Granted Dec 4, 2012·0 cites·9 claims
- 0943US2008091835A1Register/Unregister System And A Register/Unregister MethodYUAN LEI·Filed 2006·Application pending·0 cites
- 1042US8653849B2Voltage margin testing device and methodYUAN LEI·Filed 2011·Granted Feb 18, 2014·0 cites·6 claims
- 1136US2013127445A1Test fixture with loadYUAN LEI·Filed 2011·Application pending·0 cites
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