Assignee
YUZAWA TAKESHI
JP·3 granted patents·11 citations·filing 2007–2011
Top patents by PatentIndex Score
3 records- 0187US8614513B2Semiconductor device including a buffer layer structure for reducing stressYUZAWA TAKESHI·Filed 2007·Granted Dec 24, 2013·11 cites·9 claims
- 0249US8878365B2Semiconductor device having a conductive layer reliably formed under an electrode padYUZAWA TAKESHI·Filed 2011·Granted Nov 4, 2014·0 cites·6 claims
- 0344US8441125B2Semiconductor deviceYUZAWA TAKESHI·Filed 2011·Granted May 14, 2013·0 cites·9 claims
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